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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id y19si10651915pgj.37.2017.02.09.09.38.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 09:38:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2CC5D82007; Thu, 9 Feb 2017 09:38:36 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 23E6482007 for ; Thu, 9 Feb 2017 09:38:34 -0800 (PST) Received: by mail-wm0-x235.google.com with SMTP id v77so26678091wmv.0 for ; Thu, 09 Feb 2017 09:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HMVvVAeoGCU0B5PKtUAEJ91azzWCePUIyogHNAtEr3Y=; b=Fr/FQYp6m1l25MwtKzeo0sMZPM6HIxvuI6I/VHxSRXdIoneMl2VuFPqkDSB05nkbW0 LRk5wfojnxEGW7tc255tVvaJL3gosOJhQAT1IAaRQlkXNrAo2NggKk+iwAC098GdNvrS 4wk4VtuqWfq8GfjGFs6EfuTpCWx9o2WTecT40= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HMVvVAeoGCU0B5PKtUAEJ91azzWCePUIyogHNAtEr3Y=; b=eaC86JS7s3Pivv1oS/MrQoxRySXXaCoF4tZENyxzKVEd8UaS06J0fOz5iJPeRbHQ57 Vr8UrCs+AlP5o6uR9hAcwR0yNlcvSESk/lULpl/XC+Y+pP3T/+ZZWr8LaNUpJ7QTwaAQ r8ZQ0jWCrrb93137FyBUH5RQ3z8YNxVMkiWzQC+yQCzkoL6Vd+qa6zKBoOpQXGdqY6QB QB2g8/WTIT3Ki4tb0+YqldKpZ7wzzoftmMMFVnYqXpPNaVlK44hHgM4HwvbkW7ITQJRe NXfTtF58aJSavYL3PWSURPjEzJhCk5qc4tD6FxQnkUeLjcwPBYyIxDFgOMFTymBuBTmP fvJg== X-Gm-Message-State: AMke39mv9k9E5kaSLp51E1U16mwU6+OzChX5YPdknKOtwcIWC2BRHul+WmDtDusu1iGzG78d X-Received: by 10.28.34.194 with SMTP id i185mr22806442wmi.118.1486661912730; Thu, 09 Feb 2017 09:38:32 -0800 (PST) Received: from localhost.localdomain ([160.169.163.122]) by smtp.gmail.com with ESMTPSA id p49sm19530786wrb.10.2017.02.09.09.38.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Feb 2017 09:38:31 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jiewen.yao@intel.com Date: Thu, 9 Feb 2017 17:38:11 +0000 Message-Id: <1486661891-7888-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> References: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 4/4] ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.d.kinney@intel.com, feng.tian@intel.com, jeff.fan@intel.com, star.zeng@intel.com, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 73 +++++++++++++++----- 1 file changed, 56 insertions(+), 17 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 6aa970bc0514..764e54b5d747 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -28,6 +28,10 @@ // We use this index definition to define an invalid block entry #define TT_ATTR_INDX_INVALID ((UINT32)~0) +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ + EFI_MEMORY_WT | EFI_MEMORY_WB | \ + EFI_MEMORY_UCE) + STATIC UINT64 ArmMemoryAttributeToPageAttribute ( @@ -101,25 +105,46 @@ PageAttributeToGcdAttribute ( return GcdAttributes; } -ARM_MEMORY_REGION_ATTRIBUTES -GcdAttributeToArmAttribute ( +STATIC +UINT64 +GcdAttributeToPageAttribute ( IN UINT64 GcdAttributes ) { - switch (GcdAttributes & 0xFF) { + UINT64 PageAttributes; + + switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { case EFI_MEMORY_UC: - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + break; case EFI_MEMORY_WC: - return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; + break; case EFI_MEMORY_WT: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; + break; case EFI_MEMORY_WB: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; + break; default: - DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes)); - ASSERT (0); - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + PageAttributes = TT_ATTR_INDX_MASK; + break; } + + if ((GcdAttributes & EFI_MEMORY_XP) != 0 || + (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) { + if (ArmReadCurrentEL () == AARCH64_EL2) { + PageAttributes |= TT_XN_MASK; + } else { + PageAttributes |= TT_UXN_MASK | TT_PXN_MASK; + } + } + + if ((GcdAttributes & EFI_MEMORY_RO) != 0) { + PageAttributes |= TT_AP_RO_RO; + } + + return PageAttributes | TT_AF; } #define MIN_T0SZ 16 @@ -434,17 +459,31 @@ SetMemoryAttributes ( ) { RETURN_STATUS Status; - ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion; UINT64 *TranslationTable; - - MemoryRegion.PhysicalBase = BaseAddress; - MemoryRegion.VirtualBase = BaseAddress; - MemoryRegion.Length = Length; - MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes); + UINT64 PageAttributes; + UINT64 PageAttributeMask; + + PageAttributes = GcdAttributeToPageAttribute (Attributes); + PageAttributeMask = 0; + + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { + // + // No memory type was set in Attributes, so we are going to update the + // permissions only. + // + PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; + PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | + TT_PXN_MASK | TT_XN_MASK); + } TranslationTable = ArmGetTTBR0BaseAddress (); - Status = FillTranslationTable (TranslationTable, &MemoryRegion); + Status = UpdateRegionMapping ( + TranslationTable, + BaseAddress, + Length, + PageAttributes, + PageAttributeMask); if (RETURN_ERROR (Status)) { return Status; }