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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id m90si7135168qtd.98.2017.02.13.04.37.06 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Feb 2017 04:37:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdFsO-00046f-5b for patch@linaro.org; Mon, 13 Feb 2017 07:37:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53714) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cdFSS-0005Qi-Mf for qemu-devel@nongnu.org; Mon, 13 Feb 2017 07:10:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cdFSR-0002eN-9t for qemu-devel@nongnu.org; Mon, 13 Feb 2017 07:10:16 -0500 Received: from mail-wr0-x230.google.com ([2a00:1450:400c:c0c::230]:35171) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cdFSR-0002e4-4O for qemu-devel@nongnu.org; Mon, 13 Feb 2017 07:10:15 -0500 Received: by mail-wr0-x230.google.com with SMTP id 89so149109865wrr.2 for ; Mon, 13 Feb 2017 04:10:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J1xpBQjVD3DTVxiV/CC9qQCH9HfTxWdvl37XvN6Emzw=; b=JrOMk7HTVjpusy3LpdNMN65TgLtXGS+R384GY1HNAEN5ZKwHFoXY9dRCMn/IW8e+WJ hq5u916UjBhkKPplQ8Ys4MSrS4IA26mIqqrtpNQOhjawgevxwNNfIVTK2YMTLnTxMNvr 2IGQLwW1DJxu+FeWd8y34wGBrpTPbs8h0jwtY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J1xpBQjVD3DTVxiV/CC9qQCH9HfTxWdvl37XvN6Emzw=; b=RphNb8SJeiwxCRzlvtddQ/3MoaTlY9J/V0vDsvaYjhvcfV6A7A/pdkBVqCBs/2ibEC KN1IqHb+lERWguUDaGyNmh5NT7WOpVX4R1fu4P1bcAN79mxaF0EcZZ3WUGTCgJUPPhRy zYAkWuwX3VBt0CUyF+fu5ZAds4lDvB76SLgv+WD+sPBfp0FBQw/zofGXBZrBNTBqG0e/ r12qfU5Ey8gctAREzThy2Kh51GHeSK20pllGJq7oj2+llliEU3RVNwJHwW6bMQJrbAom l9O1w9Ob4dkEf1y7xeUCosrmcM50sh+vFML6MKrkxRfNINyCSUCnsQjrh0buS82tV6dX DMfQ== X-Gm-Message-State: AMke39mfrBYc2Zo77ydIIrZzZBD/UZ6rgvjQk3FwFzoeiFShkDkggJOOskt5kpfRqiimZHlD X-Received: by 10.223.151.135 with SMTP id s7mr18869243wrb.51.1486987814169; Mon, 13 Feb 2017 04:10:14 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 65sm10509866wri.53.2017.02.13.04.10.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Feb 2017 04:10:08 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 317513E0BEA; Mon, 13 Feb 2017 12:10:18 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org, rth@twiddle.net Date: Mon, 13 Feb 2017 12:10:06 +0000 Message-Id: <20170213121017.12907-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170213121017.12907-1-alex.bennee@linaro.org> References: <20170213121017.12907-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c0c::230 Subject: [Qemu-devel] [PATCH v12 13/24] cputlb: add assert_cpu_is_self checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For SoftMMU the TLB flushes are an example of a task that can be triggered on one vCPU by another. To deal with this properly we need to use safe work to ensure these changes are done safely. The new assert can be enabled while debugging to catch these cases. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- cputlb.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/cputlb.c b/cputlb.c index 1cc9d9da51..af0e65cd2c 100644 --- a/cputlb.c +++ b/cputlb.c @@ -58,6 +58,12 @@ } \ } while (0) +#define assert_cpu_is_self(this_cpu) do { \ + if (DEBUG_TLB_GATE) { \ + g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + } \ + } while (0) + /* statistics */ int tlb_flush_count; @@ -70,6 +76,9 @@ void tlb_flush(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); + tlb_debug("(count: %d)\n", tlb_flush_count++); + memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); @@ -77,13 +86,13 @@ void tlb_flush(CPUState *cpu) env->vtlb_index = 0; env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; - tlb_flush_count++; } static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("start\n"); for (;;) { @@ -128,6 +137,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) int i; int mmu_idx; + assert_cpu_is_self(cpu); tlb_debug("page :" TARGET_FMT_lx "\n", addr); /* Check if we need to flush due to large pages. */ @@ -165,6 +175,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) va_start(argp, addr); + assert_cpu_is_self(cpu); tlb_debug("addr "TARGET_FMT_lx"\n", addr); /* Check if we need to flush due to large pages. */ @@ -253,6 +264,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; + assert_cpu_is_self(cpu); + env = cpu->env_ptr; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -284,6 +297,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) int i; int mmu_idx; + assert_cpu_is_self(cpu); + vaddr &= TARGET_PAGE_MASK; i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -343,6 +358,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; int asidx = cpu_asidx_from_attrs(cpu, attrs); + assert_cpu_is_self(cpu); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size);