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[209.132.180.131]) by mx.google.com with ESMTPS id e9si1841646pgc.241.2017.02.14.15.32.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Feb 2017 15:32:29 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-137021-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-137021-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-137021-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; q=dns; s=default; b=Ryyv9Go5qt6qPKbChutA8cqVCxv+V oSNEvUTl71iC97LokEyAZHBkdH0ZeRjgbH/aTQDtE4baMdg5rATqn/x4pNZcLrZl XfGX5eHw1uoWewg3BU+0R7L9dKR2YBOy8BlCgE7Uw0+NRVDXNT37ZwtYTn/qh5W9 K+hba32RXzWFLo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; s=default; bh=V1lXGMYXaa5TcRefHYY+c9eIPuY=; b=xGo 3TDy7AHBJj/d+Q3JSwXYo3UG8ohnbrzmmp/mnc/o6ahm1hYhabtc6z/2WjI5vwpy J2G6L52cf9gdmr5N0yIb+wMJZ2UJbjwMv4hVe6gM3PZ3YGGaIg07MwLrO6Z4D9l/ EKzw+bTRkMBAUr+XkoT7iZ4q1jApY90xfmiiUV5U= Received: (qmail 52370 invoked by alias); 14 Feb 2017 23:32:20 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 52360 invoked by uid 89); 14 Feb 2017 23:32:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.0 required=5.0 tests=AWL, BAYES_50, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=instr, 1590, U*jim.wilson, jimwilsonlinaroorg X-HELO: mail-yw0-f169.google.com Received: from mail-yw0-f169.google.com (HELO mail-yw0-f169.google.com) (209.85.161.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 14 Feb 2017 23:32:10 +0000 Received: by mail-yw0-f169.google.com with SMTP id l19so74475089ywc.2 for ; Tue, 14 Feb 2017 15:32:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=U91xc6Y70+a9tGJUoocJeRiN7XUfdDzRuw85tOHg0L4=; b=VylPiRf8DPNgASGi//xkiH9Wx6Y1Ps8dyuzSof8QHGLmnY/QJQhntCXUJ+BtVpv2z8 VN6NNVu4RVTjNKBjWRJEvKSSzel0Wv+xnQSBQ5W8Nx84SiCk8qUB5PiuxBSPXXFD5LCk d12cyzYQA96nCqpwC0wldK1srzlD1euhVEsmgGA6K3gKKSYh/7NGzQumcLvuahpCOxKc 3N+VZF6Itwqif1pCRDCNofGqFYGiy21yQyABt4PzSvc3jVFwND3L8Juj45rvD8YmrPwT Da5at/JAHBhYJGpcwpGG0ID2whLpqyQRnPywKsyQ3kvyRNy3i1jc0Ci6IaYWZaWYkbu/ isaA== X-Gm-Message-State: AMke39n5q9pXm6X24UuUYmJBc7jG6w3wouwNx6/vxyhhUK6MxGx4yIO0hHtSCmHdZnLbHQkz7xU2Ha9484eTK6l/ X-Received: by 10.129.123.197 with SMTP id w188mr23482010ywc.267.1487115128362; Tue, 14 Feb 2017 15:32:08 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.37.1 with HTTP; Tue, 14 Feb 2017 15:32:07 -0800 (PST) From: Jim Wilson Date: Tue, 14 Feb 2017 15:32:07 -0800 Message-ID: Subject: [PATCH] aarch64 sim mla bug fix To: gdb-patches@sourceware.org The mla support is trying to do a widening multiply, and is also accidentally trying to write past the end of the target register. The mls support is already correct, so I replaced the mla switch body with the mls switch body, changing - to +. The testcase fails without the patch and works with the patch. This reduces gcc C testsuite unexpected failures from 1590 to 1551 (-39). I've also added myself to the sim/MAINTAINERS file as approved by Nick Clifton and Mike Frysinger. And I've self approved this patch, committing, and pushing it. Jim sim/ * MAINTAINTERS (aarch64): Add myself. sim/aarch64/ * simulator.c (do_vec_MLA): Rewrite switch body. sim/testsuite/sim/aarch64/ * mla.s: New. diff --git a/sim/ChangeLog b/sim/ChangeLog index ba946fd..6d0c5fd 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,7 @@ +2017-02-14 Jim Wilson + + * MAINTAINTERS (aarch64): Add myself. + 2016-12-14 Maciej W. Rozycki * MAINTAINERS (Maintainers for particular sims): Add myself as diff --git a/sim/MAINTAINERS b/sim/MAINTAINERS index b373f66..62887d4 100644 --- a/sim/MAINTAINERS +++ b/sim/MAINTAINERS @@ -14,6 +14,7 @@ Mike Frysinger vapier@gentoo.org Maintainers for particular sims: aarch64 Nick Clifton +aarch64 Jim Wilson arm Nick Clifton bfin Mike Frysinger cr16 M R Swami Reddy diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 7d00621..e8d66a6 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,5 +1,7 @@ 2017-02-14 Jim Wilson + * simulator.c (do_vec_MLA): Rewrite switch body. + * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 13a2b1f..7c28219 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3799,63 +3799,30 @@ do_vec_MLA (sim_cpu *cpu) switch (INSTR (23, 22)) { case 0: - { - uint16_t a[16], b[16]; - - for (i = 0; i < (full ? 16 : 8); i++) - { - a[i] = aarch64_get_vec_u8 (cpu, vn, i); - b[i] = aarch64_get_vec_u8 (cpu, vm, i); - } - - for (i = 0; i < (full ? 16 : 8); i++) - { - uint16_t v = aarch64_get_vec_u8 (cpu, vd, i); - - aarch64_set_vec_u16 (cpu, vd, i, v + (a[i] * b[i])); - } - } + for (i = 0; i < (full ? 16 : 8); i++) + aarch64_set_vec_u8 (cpu, vd, i, + aarch64_get_vec_u8 (cpu, vd, i) + + (aarch64_get_vec_u8 (cpu, vn, i) + * aarch64_get_vec_u8 (cpu, vm, i))); return; case 1: - { - uint32_t a[8], b[8]; - - for (i = 0; i < (full ? 8 : 4); i++) - { - a[i] = aarch64_get_vec_u16 (cpu, vn, i); - b[i] = aarch64_get_vec_u16 (cpu, vm, i); - } - - for (i = 0; i < (full ? 8 : 4); i++) - { - uint32_t v = aarch64_get_vec_u16 (cpu, vd, i); - - aarch64_set_vec_u32 (cpu, vd, i, v + (a[i] * b[i])); - } - } + for (i = 0; i < (full ? 8 : 4); i++) + aarch64_set_vec_u16 (cpu, vd, i, + aarch64_get_vec_u16 (cpu, vd, i) + + (aarch64_get_vec_u16 (cpu, vn, i) + * aarch64_get_vec_u16 (cpu, vm, i))); return; case 2: - { - uint64_t a[4], b[4]; - - for (i = 0; i < (full ? 4 : 2); i++) - { - a[i] = aarch64_get_vec_u32 (cpu, vn, i); - b[i] = aarch64_get_vec_u32 (cpu, vm, i); - } - - for (i = 0; i < (full ? 4 : 2); i++) - { - uint64_t v = aarch64_get_vec_u32 (cpu, vd, i); - - aarch64_set_vec_u64 (cpu, vd, i, v + (a[i] * b[i])); - } - } + for (i = 0; i < (full ? 4 : 2); i++) + aarch64_set_vec_u32 (cpu, vd, i, + aarch64_get_vec_u32 (cpu, vd, i) + + (aarch64_get_vec_u32 (cpu, vn, i) + * aarch64_get_vec_u32 (cpu, vm, i))); return; - case 3: + default: HALT_UNALLOC; } } diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog index d47abc5..a17b977 100644 --- a/sim/testsuite/sim/aarch64/ChangeLog +++ b/sim/testsuite/sim/aarch64/ChangeLog @@ -1,5 +1,7 @@ 2017-02-14 Jim Wilson + * mla.s: New. + * bit.s: New. * ldn_single.s: New. diff --git a/sim/testsuite/sim/aarch64/mla.s b/sim/testsuite/sim/aarch64/mla.s new file mode 100644 index 0000000..e0065e7 --- /dev/null +++ b/sim/testsuite/sim/aarch64/mla.s @@ -0,0 +1,103 @@ +# mach: aarch64 + +# Check the vector multiply add instruction: mla. + +.include "testutils.inc" + +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0x110a0502 + .word 0x4132251a +m16b: + .word 0x110a0502 + .word 0x4132251a + .word 0x917a6552 + .word 0x01e2c5aa +m4h: + .word 0x180a0402 + .word 0x70323c1a +m8h: + .word 0x180a0402 + .word 0x70323c1a + .word 0x087ab452 + .word 0xe0e26caa +m2s: + .word 0x140a0402 + .word 0xa46a3c1a +m4s: + .word 0x140a0402 + .word 0xa46a3c1a + .word 0xb52ab452 + .word 0x464b6caa + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + movi v1.8b, #1 + mla v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x3, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + movi v1.16b, #1 + mla v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x3, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + movi v1.4h, #1 + mla v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x3, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + movi v1.8h, #1 + mla v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x3, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + movi v1.2s, #1 + mla v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x3, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + movi v1.4s, #1 + mla v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x3, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail