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[54.225.227.206]) by mx.google.com with ESMTP id d39si2982558qtf.224.2017.02.15.06.55.32; Wed, 15 Feb 2017 06:55:33 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7CF1062D3B; Wed, 15 Feb 2017 14:55:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 2F64A62D90; Wed, 15 Feb 2017 14:55:16 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6DB1262CFE; Wed, 15 Feb 2017 14:55:12 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id 0545E60C29 for ; Wed, 15 Feb 2017 14:55:10 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id 189so32173306pfu.3 for ; Wed, 15 Feb 2017 06:55:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cI+Yl39btELp2qS4hRBQ7Zn2WSc/5rqW5bpIsMSC6y0=; b=qdthzQvGtnkg0jxu2wJBTMnxg6fA1nebPXB7ZC0v/kNoZQFXlegK1BRQewvvhKhf5s ofWd59WctImP2ywOws31/aJ6dbLbsMnJaQCEFCnnvB+CxJ63nnCAILf6Xp41LAVPBMn9 0pRtmBRmJSIXlwRYb6Tpn+Sm3N0vAwT6QgMBmDDoNgLR+CqqDINkWuhMB1JQQPvn8OSh rNXM58rBU49EEvUC0XqtMe7IifRIG8WoIPvW8UbRFGUNQOrHOMF3CxuIQahMdpUcev6t 9zSTnGLbiQIntgtf2q/g0ZtC3zXSPwk1mEqFx/v1I/+4BDtGC8resAOI2td0lnXFk3he vj3Q== X-Gm-Message-State: AMke39kGPxqf8w5yF3rBtYu5/0+NIY9vpvJTDJ49GsAWhKr3IjtBeCfn2uSNxZxokrFs7I4nsNw= X-Received: by 10.84.216.93 with SMTP id f29mr24033764plj.10.1487170509316; Wed, 15 Feb 2017 06:55:09 -0800 (PST) Received: from localhost.localdomain ([45.56.159.211]) by smtp.gmail.com with ESMTPSA id s24sm8212782pgo.25.2017.02.15.06.55.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 06:55:08 -0800 (PST) From: Haojian Zhuang To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Wed, 15 Feb 2017 22:54:55 +0800 Message-Id: <1487170499-22374-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487170499-22374-1-git-send-email-haojian.zhuang@linaro.org> References: <1487170499-22374-1-git-send-email-haojian.zhuang@linaro.org> Subject: [Linaro-uefi] [PATCH v4 1/5] Platforms/Hisilicon/HiKey: append more register definitions X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add more register definitions in Hi6220 SoC. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Hi6220/Include/Hi6220.h | 54 +++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/Chips/Hisilicon/Hi6220/Include/Hi6220.h b/Chips/Hisilicon/Hi6220/Include/Hi6220.h index 203424a..248de00 100644 --- a/Chips/Hisilicon/Hi6220/Include/Hi6220.h +++ b/Chips/Hisilicon/Hi6220/Include/Hi6220.h @@ -23,6 +23,23 @@ #define HI6220_PERIPH_BASE 0xF4000000 #define HI6220_PERIPH_SZ 0x05800000 +#define GPIO4_CTRL_BASE 0xF7020000 +#define GPIO5_CTRL_BASE 0xF7021000 +#define GPIO6_CTRL_BASE 0xF7022000 +#define GPIO7_CTRL_BASE 0xF7023000 +#define GPIO8_CTRL_BASE 0xF7024000 +#define GPIO9_CTRL_BASE 0xF7025000 +#define GPIO10_CTRL_BASE 0xF7026000 +#define GPIO11_CTRL_BASE 0xF7027000 +#define GPIO12_CTRL_BASE 0xF7028000 +#define GPIO13_CTRL_BASE 0xF7029000 +#define GPIO14_CTRL_BASE 0xF702A000 +#define GPIO15_CTRL_BASE 0xF702B000 +#define GPIO16_CTRL_BASE 0xF702C000 +#define GPIO17_CTRL_BASE 0xF702D000 +#define GPIO18_CTRL_BASE 0xF702E000 +#define GPIO19_CTRL_BASE 0xF702F000 + #define PERI_CTRL_BASE 0xF7030000 #define SC_PERIPH_CTRL4 0x00C #define CTRL4_FPGA_EXT_PHY_SEL BIT3 @@ -45,18 +62,47 @@ #define SC_PERIPH_CTRL8 0x018 #define SC_PERIPH_CLKEN0 0x200 + +#define PERIPH_CLKEN0_USBOTG BIT4 + #define SC_PERIPH_CLKDIS0 0x204 #define SC_PERIPH_CLKSTAT0 0x208 +#define SC_PERIPH_CLKEN3 0x230 #define SC_PERIPH_RSTEN0 0x300 #define SC_PERIPH_RSTDIS0 0x304 #define SC_PERIPH_RSTSTAT0 0x308 +#define SC_PERIPH_RSTEN3 0x330 +#define SC_PERIPH_RSTDIS3 0x334 +#define SC_PERIPH_RSTSTAT3 0x338 #define RST0_USBOTG_BUS BIT4 #define RST0_POR_PICOPHY BIT5 #define RST0_USBOTG BIT6 #define RST0_USBOTG_32K BIT7 +/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ +#define PERIPH_RST0_MMC2 (1 << 2) + +/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ +#define PERIPH_RST3_CSSYS (1 << 0) +#define PERIPH_RST3_I2C0 (1 << 1) +#define PERIPH_RST3_I2C1 (1 << 2) +#define PERIPH_RST3_I2C2 (1 << 3) +#define PERIPH_RST3_I2C3 (1 << 4) +#define PERIPH_RST3_UART1 (1 << 5) +#define PERIPH_RST3_UART2 (1 << 6) +#define PERIPH_RST3_UART3 (1 << 7) +#define PERIPH_RST3_UART4 (1 << 8) +#define PERIPH_RST3_SSP (1 << 9) +#define PERIPH_RST3_PWM (1 << 10) +#define PERIPH_RST3_BLPWM (1 << 11) +#define PERIPH_RST3_TSENSOR (1 << 12) +#define PERIPH_RST3_DAPB (1 << 18) +#define PERIPH_RST3_HKADC (1 << 19) +#define PERIPH_RST3_CODEC_SSI (1 << 20) +#define PERIPH_RST3_PMUSSI1 (1 << 22) + #define EYE_PATTERN_PARA 0x7053348c #define MDDRC_AXI_BASE 0xF7120000 @@ -74,4 +120,12 @@ #define PMUSSI_BASE 0xF8000000 +#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) + +#define GPIO0_CTRL_BASE 0xF8011000 +#define GPIO1_CTRL_BASE 0xF8012000 +#define GPIO2_CTRL_BASE 0xF8013000 +#define GPIO3_CTRL_BASE 0xF8014000 + + #endif /* __HI6220_H__ */