diff mbox series

[11/11] stm32f205: Rename 'nvic' local to 'armv7m'

Message ID 1487604965-23220-12-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show
Series ARMv7M: QOMify | expand

Commit Message

Peter Maydell Feb. 20, 2017, 3:36 p.m. UTC 
The local variable 'nvic' in stm32f205_soc_realize() no longer
holds a direct pointer to the NVIC device; it is a pointer to
the ARMv7M container object. Rename it 'armv7m' accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/arm/stm32f205_soc.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

-- 
2.7.4

Comments

Philippe Mathieu-Daudé Feb. 20, 2017, 5:46 p.m. UTC | #1 
On 02/20/2017 12:36 PM, Peter Maydell wrote:
> The local variable 'nvic' in stm32f205_soc_realize() no longer

> holds a direct pointer to the NVIC device; it is a pointer to

> the ARMv7M container object. Rename it 'armv7m' accordingly.

>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> ---

>  hw/arm/stm32f205_soc.c | 18 +++++++++---------

>  1 file changed, 9 insertions(+), 9 deletions(-)

>

> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c

> index e6bd73a..6e1260d 100644

> --- a/hw/arm/stm32f205_soc.c

> +++ b/hw/arm/stm32f205_soc.c

> @@ -85,7 +85,7 @@ static void stm32f205_soc_initfn(Object *obj)

>  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>  {

>      STM32F205State *s = STM32F205_SOC(dev_soc);

> -    DeviceState *dev, *nvic;

> +    DeviceState *dev, *armv7m;

>      SysBusDevice *busdev;

>      Error *err = NULL;

>      int i;

> @@ -113,9 +113,9 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>      vmstate_register_ram_global(sram);

>      memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);

>

> -    nvic = DEVICE(&s->armv7m);

> -    qdev_prop_set_uint32(nvic, "num-irq", 96);

> -    qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);

> +    armv7m = DEVICE(&s->armv7m);

> +    qdev_prop_set_uint32(armv7m, "num-irq", 96);

> +    qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);

>      object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),

>                                       "memory", &error_abort);

>      object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

> @@ -133,7 +133,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>      }

>      busdev = SYS_BUS_DEVICE(dev);

>      sysbus_mmio_map(busdev, 0, 0x40013800);

> -    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));

> +    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));

>

>      /* Attach UART (uses USART registers) and USART controllers */

>      for (i = 0; i < STM_NUM_USARTS; i++) {

> @@ -147,7 +147,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          }

>          busdev = SYS_BUS_DEVICE(dev);

>          sysbus_mmio_map(busdev, 0, usart_addr[i]);

> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));

> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));

>      }

>

>      /* Timer 2 to 5 */

> @@ -161,7 +161,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          }

>          busdev = SYS_BUS_DEVICE(dev);

>          sysbus_mmio_map(busdev, 0, timer_addr[i]);

> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));

> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));

>      }

>

>      /* ADC 1 to 3 */

> @@ -173,7 +173,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          return;

>      }

>      qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,

> -                          qdev_get_gpio_in(nvic, ADC_IRQ));

> +                          qdev_get_gpio_in(armv7m, ADC_IRQ));

>

>      for (i = 0; i < STM_NUM_ADCS; i++) {

>          dev = DEVICE(&(s->adc[i]));

> @@ -198,7 +198,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          }

>          busdev = SYS_BUS_DEVICE(dev);

>          sysbus_mmio_map(busdev, 0, spi_addr[i]);

> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));

> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));

>      }

>  }

>

>
Alistair Francis Feb. 21, 2017, 11:34 a.m. UTC | #2 
On Mon, Feb 20, 2017 at 9:46 AM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 02/20/2017 12:36 PM, Peter Maydell wrote:

>>

>> The local variable 'nvic' in stm32f205_soc_realize() no longer

>> holds a direct pointer to the NVIC device; it is a pointer to

>> the ARMv7M container object. Rename it 'armv7m' accordingly.

>>

>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

>

>

> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>


Thanks,

Alistair

>

>

>> ---

>>  hw/arm/stm32f205_soc.c | 18 +++++++++---------

>>  1 file changed, 9 insertions(+), 9 deletions(-)

>>

>> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c

>> index e6bd73a..6e1260d 100644

>> --- a/hw/arm/stm32f205_soc.c

>> +++ b/hw/arm/stm32f205_soc.c

>> @@ -85,7 +85,7 @@ static void stm32f205_soc_initfn(Object *obj)

>>  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>>  {

>>      STM32F205State *s = STM32F205_SOC(dev_soc);

>> -    DeviceState *dev, *nvic;

>> +    DeviceState *dev, *armv7m;

>>      SysBusDevice *busdev;

>>      Error *err = NULL;

>>      int i;

>> @@ -113,9 +113,9 @@ static void stm32f205_soc_realize(DeviceState

>> *dev_soc, Error **errp)

>>      vmstate_register_ram_global(sram);

>>      memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);

>>

>> -    nvic = DEVICE(&s->armv7m);

>> -    qdev_prop_set_uint32(nvic, "num-irq", 96);

>> -    qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);

>> +    armv7m = DEVICE(&s->armv7m);

>> +    qdev_prop_set_uint32(armv7m, "num-irq", 96);

>> +    qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);

>>      object_property_set_link(OBJECT(&s->armv7m),

>> OBJECT(get_system_memory()),

>>                                       "memory", &error_abort);

>>      object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

>> @@ -133,7 +133,7 @@ static void stm32f205_soc_realize(DeviceState

>> *dev_soc, Error **errp)

>>      }

>>      busdev = SYS_BUS_DEVICE(dev);

>>      sysbus_mmio_map(busdev, 0, 0x40013800);

>> -    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));

>> +    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));

>>

>>      /* Attach UART (uses USART registers) and USART controllers */

>>      for (i = 0; i < STM_NUM_USARTS; i++) {

>> @@ -147,7 +147,7 @@ static void stm32f205_soc_realize(DeviceState

>> *dev_soc, Error **errp)

>>          }

>>          busdev = SYS_BUS_DEVICE(dev);

>>          sysbus_mmio_map(busdev, 0, usart_addr[i]);

>> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic,

>> usart_irq[i]));

>> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,

>> usart_irq[i]));

>>      }

>>

>>      /* Timer 2 to 5 */

>> @@ -161,7 +161,7 @@ static void stm32f205_soc_realize(DeviceState

>> *dev_soc, Error **errp)

>>          }

>>          busdev = SYS_BUS_DEVICE(dev);

>>          sysbus_mmio_map(busdev, 0, timer_addr[i]);

>> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic,

>> timer_irq[i]));

>> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,

>> timer_irq[i]));

>>      }

>>

>>      /* ADC 1 to 3 */

>> @@ -173,7 +173,7 @@ static void stm32f205_soc_realize(DeviceState

>> *dev_soc, Error **errp)

>>          return;

>>      }

>>      qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,

>> -                          qdev_get_gpio_in(nvic, ADC_IRQ));

>> +                          qdev_get_gpio_in(armv7m, ADC_IRQ));

>>

>>      for (i = 0; i < STM_NUM_ADCS; i++) {

>>          dev = DEVICE(&(s->adc[i]));

>> @@ -198,7 +198,7 @@ static void stm32f205_soc_realize(DeviceState

>> *dev_soc, Error **errp)

>>          }

>>          busdev = SYS_BUS_DEVICE(dev);

>>          sysbus_mmio_map(busdev, 0, spi_addr[i]);

>> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic,

>> spi_irq[i]));

>> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m,

>> spi_irq[i]));

>>      }

>>  }

>>

>>

>
Alex Bennée Feb. 28, 2017, 2:10 p.m. UTC | #3 
Peter Maydell <peter.maydell@linaro.org> writes:

> The local variable 'nvic' in stm32f205_soc_realize() no longer

> holds a direct pointer to the NVIC device; it is a pointer to

> the ARMv7M container object. Rename it 'armv7m' accordingly.

>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  hw/arm/stm32f205_soc.c | 18 +++++++++---------

>  1 file changed, 9 insertions(+), 9 deletions(-)

>

> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c

> index e6bd73a..6e1260d 100644

> --- a/hw/arm/stm32f205_soc.c

> +++ b/hw/arm/stm32f205_soc.c

> @@ -85,7 +85,7 @@ static void stm32f205_soc_initfn(Object *obj)

>  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>  {

>      STM32F205State *s = STM32F205_SOC(dev_soc);

> -    DeviceState *dev, *nvic;

> +    DeviceState *dev, *armv7m;

>      SysBusDevice *busdev;

>      Error *err = NULL;

>      int i;

> @@ -113,9 +113,9 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>      vmstate_register_ram_global(sram);

>      memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);

>

> -    nvic = DEVICE(&s->armv7m);

> -    qdev_prop_set_uint32(nvic, "num-irq", 96);

> -    qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);

> +    armv7m = DEVICE(&s->armv7m);

> +    qdev_prop_set_uint32(armv7m, "num-irq", 96);

> +    qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);

>      object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),

>                                       "memory", &error_abort);

>      object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

> @@ -133,7 +133,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>      }

>      busdev = SYS_BUS_DEVICE(dev);

>      sysbus_mmio_map(busdev, 0, 0x40013800);

> -    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));

> +    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));

>

>      /* Attach UART (uses USART registers) and USART controllers */

>      for (i = 0; i < STM_NUM_USARTS; i++) {

> @@ -147,7 +147,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          }

>          busdev = SYS_BUS_DEVICE(dev);

>          sysbus_mmio_map(busdev, 0, usart_addr[i]);

> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));

> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));

>      }

>

>      /* Timer 2 to 5 */

> @@ -161,7 +161,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          }

>          busdev = SYS_BUS_DEVICE(dev);

>          sysbus_mmio_map(busdev, 0, timer_addr[i]);

> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));

> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));

>      }

>

>      /* ADC 1 to 3 */

> @@ -173,7 +173,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          return;

>      }

>      qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,

> -                          qdev_get_gpio_in(nvic, ADC_IRQ));

> +                          qdev_get_gpio_in(armv7m, ADC_IRQ));

>

>      for (i = 0; i < STM_NUM_ADCS; i++) {

>          dev = DEVICE(&(s->adc[i]));

> @@ -198,7 +198,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)

>          }

>          busdev = SYS_BUS_DEVICE(dev);

>          sysbus_mmio_map(busdev, 0, spi_addr[i]);

> -        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));

> +        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));

>      }

>  }



--
Alex Bennée
diff mbox series

Patch

diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index e6bd73a..6e1260d 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -85,7 +85,7 @@  static void stm32f205_soc_initfn(Object *obj)
 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     STM32F205State *s = STM32F205_SOC(dev_soc);
-    DeviceState *dev, *nvic;
+    DeviceState *dev, *armv7m;
     SysBusDevice *busdev;
     Error *err = NULL;
     int i;
@@ -113,9 +113,9 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
     vmstate_register_ram_global(sram);
     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 
-    nvic = DEVICE(&s->armv7m);
-    qdev_prop_set_uint32(nvic, "num-irq", 96);
-    qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 96);
+    qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
     object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
                                      "memory", &error_abort);
     object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
@@ -133,7 +133,7 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
     }
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_mmio_map(busdev, 0, 0x40013800);
-    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
+    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
 
     /* Attach UART (uses USART registers) and USART controllers */
     for (i = 0; i < STM_NUM_USARTS; i++) {
@@ -147,7 +147,7 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, usart_addr[i]);
-        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
     }
 
     /* Timer 2 to 5 */
@@ -161,7 +161,7 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, timer_addr[i]);
-        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
     }
 
     /* ADC 1 to 3 */
@@ -173,7 +173,7 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
-                          qdev_get_gpio_in(nvic, ADC_IRQ));
+                          qdev_get_gpio_in(armv7m, ADC_IRQ));
 
     for (i = 0; i < STM_NUM_ADCS; i++) {
         dev = DEVICE(&(s->adc[i]));
@@ -198,7 +198,7 @@  static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
         }
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, spi_addr[i]);
-        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
     }
 }