From patchwork Tue Jun 19 07:30:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9438 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3283B23F19 for ; Tue, 19 Jun 2012 07:26:07 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 02289A181AA for ; Tue, 19 Jun 2012 07:26:06 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so4759166ggn.11 for ; Tue, 19 Jun 2012 00:26:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=9jDe/6GnJkutFU55IUNVBipdK0MUJ11v86LVFaPE/t0=; b=HhGTCban//I4VQ5bgZVg8i6H8uB4lfvX3NVtN1Qm8fP8n8ht7Og7v5kt6eAPC8rkvz JXBrh0TK6BxPP2vIUrpYICuG9pJg2sQbMhBau9j6ENWT5xnv558VfUOvE4e4D2CKCnwD OdiHeeQMGXpwNulE8ZDT2VBZ0coTgOIEFAxDCD+wVuU/S7rATXLNSINlEVYogpAh6eec jYOHpz8TwzGSHqutJtE09QF5lEWJcdzE0Ob2fGKYBY6xS8XEBYUQmj95GNPkEhZNHfHB wGYvp3HI5hM0j8V3VtU1A212dA6oaoMYWWU9Yhc04ODvzqVmfOWoivKC8jcKrY9RxD5U CFuQ== Received: by 10.50.57.167 with SMTP id j7mr197139igq.53.1340090766633; Tue, 19 Jun 2012 00:26:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp110427ibb; Tue, 19 Jun 2012 00:26:06 -0700 (PDT) Received: by 10.68.237.74 with SMTP id va10mr60807356pbc.46.1340090765848; Tue, 19 Jun 2012 00:26:05 -0700 (PDT) Received: from mailout3.samsung.com (mailout3.samsung.com. [203.254.224.33]) by mx.google.com with ESMTP id sp1si28569936pbc.140.2012.06.19.00.26.05; Tue, 19 Jun 2012 00:26:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5U00B2ZSMRA380@mailout3.samsung.com>; Tue, 19 Jun 2012 16:26:04 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-2f-4fe0298c74eb Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 95.D2.05800.C8920EF4; Tue, 19 Jun 2012 16:26:04 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5U00EHGSMYFC70@mmp1.samsung.com>; Tue, 19 Jun 2012 16:26:04 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com Subject: [PATCH 3/8 V4] EXYNOS: PINMUX: Add pinmux support for I2C Date: Tue, 19 Jun 2012 13:00:27 +0530 Message-id: <1340091032-26560-4-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340091032-26560-1-git-send-email-rajeshwari.s@samsung.com> References: <1340091032-26560-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jAd0ezQf+Bk/2CVs8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK+HuljbXgt0TF+eUtjA2MH0W6GDk5JARMJA5N+sEI YYtJXLi3nq2LkYtDSGARo8S5t3tYIZyJTBI7D/8Hq2ITMJLYenIamC0iICHxq/8qmM0sMIVR Ytfq0C5GDg5hASeJQ7OiQMIsAqoS3Yu3MIHYvAIeEota7jJDLFOQODb1KyuIzSngKTFp/3yw GiGgmvtfzjFNYORdwMiwilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyPY+8+kdjCubLA4xCjA wajEw3tQ7oG/EGtiWXFl7iFGCQ5mJRHeVf/v+wvxpiRWVqUW5ccXleakFh9ilOZgURLnbbK+ 4C8kkJ5YkpqdmlqQWgSTZeLglGpg3FOX1bElTqis75jDt+rVKUkl8cKLPS4ttp0k+OmSgVa5 9W6uKdN0bCXvJLV39ijYKypd+/PuccHts4fjlaMsv/CJPk4Nujg38b7qRZM1F3smXEqdtuxz 7837h5/5B25dLGYudm177RHG9nNtL5x71rl9t1FnXvSx+cWMk38feIcqbeZln7w0VImlOCPR UIu5qDgRAF1gCFf6AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQl1vHTiTuCDG8l2bcve0QaObSlp2WeMkN3IaXwKBntUz4Y6TzOXyomk385mP+6jLJ5Bn+0P This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - Aligned the pinmux functionality as per the latest comments. Changes in V3: - None Changes in V4: - None arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 8 ++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..d28f055 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -184,6 +184,48 @@ static void exynos5_sromc_config(int flags) } } +static void exynos5_i2c_config(int peripheral, int flags) +{ + + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + + switch (peripheral) { + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + break; + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -201,6 +243,16 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SROMC: exynos5_sromc_config(flags); break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos5_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 5db25aa..b861d7d 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -30,6 +30,14 @@ * */ enum periph_id { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, PERIPH_ID_SDMMC0, PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2,