From patchwork Fri Feb 24 09:06:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 94426 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp602092qgi; Fri, 24 Feb 2017 01:16:19 -0800 (PST) X-Received: by 10.98.153.25 with SMTP id d25mr2197142pfe.15.1487927779102; Fri, 24 Feb 2017 01:16:19 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a36si6850054pli.42.2017.02.24.01.16.18; Fri, 24 Feb 2017 01:16:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751471AbdBXJQM (ORCPT + 7 others); Fri, 24 Feb 2017 04:16:12 -0500 Received: from mail-pg0-f41.google.com ([74.125.83.41]:35137 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751455AbdBXJQA (ORCPT ); Fri, 24 Feb 2017 04:16:00 -0500 Received: by mail-pg0-f41.google.com with SMTP id b129so9370175pgc.2 for ; Fri, 24 Feb 2017 01:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=f2gUkTr+FpJ8k1EggBgzG8SC1jYs5txBsC/VIfRZfVQ=; b=H48y31S1rrC+wSPGM92kumoGSEJvrn04RXhiJFERDqmuiMuLzPwbfB+RyygmCkX8BA JwdH3GxBR/IbdJSwjmU5kTUO7LVRwtbVO/1uvasY/7Tx7fmQole19EpFmuwLxbUuVDs1 08LoKgUfsI4vw7EQqw3aF8mU6MMFcK6RNnyTs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=f2gUkTr+FpJ8k1EggBgzG8SC1jYs5txBsC/VIfRZfVQ=; b=ZoDdbnynOFb+pzNOJ9e5Mo5pOWS4danuAbQKpLlWrUNdIUzU1HhkNqOq0kAUNw3N4/ lNzSrjEuaQjOmtXqkbqpcd6Zd1IbHqs2YG5xETEwGvHJdNivgvORdtAiZ/VsfgEBssjh Xf8YnSfUKfxvfP+bxKL45ftQrWZPqGpjtBgk8fLlTbhnNWjBH6IlmXi3IVZKm/c4Xzl3 LCc6Gh6sfs7CGBwuli41Tovyhx8LErbWWM7plM4bgV+E6SkG6s97BDe2/XKcUrDSaGxc hS6nMpQoiyi+4Yr1omYaye2e0JlZv2mlLwXlwphrrZZtoXoW5517qFgJrP/pIrorFQzH Af6Q== X-Gm-Message-State: AMke39lMtcZWd21/40p4H4cJzfSYt2J6O+1H2THkHwosI0FxUjL1V0TJuXSBLqqDSAl3ETuX X-Received: by 10.84.197.3 with SMTP id m3mr2320182pld.89.1487927211796; Fri, 24 Feb 2017 01:06:51 -0800 (PST) Received: from localhost ([122.172.165.189]) by smtp.gmail.com with ESMTPSA id r134sm13905900pfr.83.2017.02.24.01.06.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Feb 2017 01:06:51 -0800 (PST) From: Viresh Kumar To: Rafael Wysocki , ulf.hansson@linaro.org, Kevin Hilman , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Vincent Guittot , robh+dt@kernel.org, lina.iyer@linaro.org, rnayak@codeaurora.org, Viresh Kumar , devicetree@vger.kernel.org Subject: [PATCH V3 2/7] PM / OPP: Introduce "domain-performance-state" binding to OPP nodes Date: Fri, 24 Feb 2017 14:36:34 +0530 Message-Id: X-Mailer: git-send-email 2.7.1.410.g6faf27b In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org If the consumers don't need the capability of switching to different domain performance states at runtime, then they can simply define their required domain performance state in their nodes directly. But if the device needs the capability of switching to different domain performance states, as they may need to support different clock rates, then the per OPP node can be used to contain that information. This patch introduces the domain-performance-state (already defined by Power Domain bindings) to the per OPP node. Signed-off-by: Viresh Kumar Tested-by: Rajendra Nayak --- Documentation/devicetree/bindings/opp/opp.txt | 64 +++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.7.1.410.g6faf27b -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index 9f5ca4457b5f..7f6bb52521b6 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -154,6 +154,15 @@ properties. - status: Marks the node enabled/disabled. +- domain-performance-state: A positive integer value representing the minimum + performance level (of the parent domain) required by the consumer as defined + by ../power/power_domain.txt binding document. The OPP nodes can contain the + "domain-performance-state" property, only if the device node contains a + "power-domains" property. The OPP nodes aren't allowed to contain the + "domain-performance-state" property partially, i.e. Either all OPP nodes in + the OPP table have the "domain-performance-state" property or none of them + have it. + Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. / { @@ -528,3 +537,58 @@ Example 5: opp-supported-hw }; }; }; + +Example 7: domain-Performance-state: +(example: For 1GHz require domain state 1 and for 1.1 & 1.2 GHz require state 2) + +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + domain-performance-state = <1>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + domain-performance-state = <2>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + domain-performance-state = <2>; + }; + }; + + foo_domain: power-controller@12340000 { + compatible = "foo,power-controller"; + reg = <0x12340000 0x1000>; + #power-domain-cells = <0>; + + performance-states { + compatible = "domain-performance-state"; + pstate@1 { + reg = <1>; + domain-microvolt = <970000 975000 985000>; + }; + pstate@2 { + reg = <2>; + domain-microvolt = <1000000 1075000 1085000>; + }; + }; + } + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&foo_domain>; + }; + }; +};