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[203.254.224.33]) by mx.google.com with ESMTP id gk6si33872247pbc.344.2012.06.20.03.36.40; Wed, 20 Jun 2012 03:36:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00C7FW4BEW50@mailout3.samsung.com>; Wed, 20 Jun 2012 19:36:40 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-29-4fe1a7b7c9d3 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 8F.E7.05800.7B7A1EF4; Wed, 20 Jun 2012 19:36:40 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00HP6W2XTK70@mmp1.samsung.com>; Wed, 20 Jun 2012 19:36:39 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com, banajit.g@samsung.com Subject: [PATCH 7/9] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 Date: Wed, 20 Jun 2012 16:10:08 +0530 Message-id: <1340188810-18871-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> References: <1340188810-18871-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAd0dyx/6GyyYymzxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoEr4/KV00wFK/kq1r29yNjAeI+7i5GDQ0LARGLmd74u Rk4gU0ziwr31bF2MXBxCAosYJZ5u+ckK4Uxkknjddp4NpIpNwEhi68lpjCC2iICExK/+q4wg RcwCCxklJsy8yQySEBYIlpi84C5YEYuAqsSpGU1MIDavgIfEvlsTGSHWKUgcm/qVFcTmFPCU mHZmFwuILQRU8/z8JfYJjLwLGBlWMYqmFiQXFCel5xrqFSfmFpfmpesl5+duYgT7/5nUDsaV DRaHGAU4GJV4eHlmP/QXYk0sK67MPcQowcGsJMJb3gEU4k1JrKxKLcqPLyrNSS0+xCjNwaIk zttkfcFfSCA9sSQ1OzW1ILUIJsvEwSnVwJg3u+3VhVzBLvt6hdyer+HTHDSMFgp2/F4TLup0 8vaxuZmX9u5dr688v/fgLbeqqCt+uXqr2Oouze1b37lK/mUlo3C9J2v+pLMpX1e9yTyxxrw6 QSR5ideru97SD2e8zj20sOFDXfvdtMWTlHvUeNTPzrr9hm2C+bZ/515wN+w5Exe312TFovdK LMUZiYZazEXFiQDWVOSa+wEAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkca7PMmnEPU65daCl7bRZ6rjAH45+fBD6ZN1wQNZs8r/IYKgcPcQEHvDQSw69jStPGwYiA MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 7cc3d5e..a34a3f0 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -594,4 +594,7 @@ struct exynos5_clock { unsigned char res109b[0xf5e4]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif