From patchwork Tue Mar 7 09:52:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 94962 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1810902qgd; Tue, 7 Mar 2017 01:57:46 -0800 (PST) X-Received: by 10.98.21.71 with SMTP id 68mr26886345pfv.16.1488880666756; Tue, 07 Mar 2017 01:57:46 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r17si22010514pgg.388.2017.03.07.01.57.46; Tue, 07 Mar 2017 01:57:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754955AbdCGJ5n (ORCPT + 4 others); Tue, 7 Mar 2017 04:57:43 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:33041 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754611AbdCGJ5h (ORCPT ); Tue, 7 Mar 2017 04:57:37 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v279rfYa007268; Tue, 7 Mar 2017 03:53:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488880421; bh=sEPRJb95mLwtOM2X9KlOcd7BAdOkR2HmJN6aPZDO5n8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=W8z4oioFSJFXGa5qVcVoW+cIf0u05xf2B2vElzqhRy5mYxvwY+drNNFffo1/k8L27 Jkf5+PhKVwkhnwilrETWV0WT64PT6JkdsLcPgVKUkloU3oZthrKrgJsuJg5af82Zgw gg/ZXPGi42vM1z2qNI8v2ZUxgu2WvmLeyDQBjNIQ= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v279rfqe012998; Tue, 7 Mar 2017 03:53:41 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 7 Mar 2017 03:53:40 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v279qsZb011421; Tue, 7 Mar 2017 03:53:37 -0600 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , Kishon Vijay Abraham I Subject: [PATCH v2 6/7] PCI: dwc: designware: Modify _unroll() to _ob_unroll() Date: Tue, 7 Mar 2017 15:22:51 +0530 Message-ID: <1488880372-7390-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1488880372-7390-1-git-send-email-kishon@ti.com> References: <1488880372-7390-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. This will enable to seamlessly add functions for inbound configurations required for endpoint mode. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 51 ++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 24 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 557ee53..006afba 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -92,16 +92,16 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "write DBI address failed\n"); } -static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, void __iomem *base, - u32 index, u32 reg) +static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); return dw_pcie_read_dbi(pci, base, offset + reg, 0x4); } -static void dw_pcie_writel_unroll(struct dw_pcie *pci, void __iomem *base, - u32 index, u32 reg, u32 val) +static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, void __iomem *base, + u32 index, u32 reg, u32 val) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); @@ -118,24 +118,26 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); if (pci->iatu_unroll_enabled) { - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LOWER_BASE, - lower_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_UPPER_BASE, - upper_32_bits(cpu_addr)); - dw_pcie_writel_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, - lower_32_bits(cpu_addr + size - 1)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_LOWER_TARGET, - lower_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_UPPER_TARGET, - upper_32_bits(pci_addr)); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL1, - type); - dw_pcie_writel_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL2, - PCIE_ATU_ENABLE); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pci_addr)); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL1, + type); + dw_pcie_writel_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); } else { dw_pcie_write_dbi(pci, base, PCIE_ATU_VIEWPORT, 0x4, PCIE_ATU_REGION_OUTBOUND | index); @@ -160,8 +162,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { if (pci->iatu_unroll_enabled) - val = dw_pcie_readl_unroll(pci, base, index, - PCIE_ATU_UNR_REGION_CTRL2); + val = + dw_pcie_readl_ob_unroll(pci, base, index, + PCIE_ATU_UNR_REGION_CTRL2); else val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);