From patchwork Mon Mar 13 13:04:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95221 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1165258qgd; Mon, 13 Mar 2017 06:11:47 -0700 (PDT) X-Received: by 10.28.45.212 with SMTP id t203mr9571320wmt.37.1489410707085; Mon, 13 Mar 2017 06:11:47 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id z64si585574wrc.261.2017.03.13.06.11.46; Mon, 13 Mar 2017 06:11:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 99967C21C8D; Mon, 13 Mar 2017 13:08:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F1B9EC21C61; Mon, 13 Mar 2017 13:08:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 38919C21C51; Mon, 13 Mar 2017 13:06:28 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 179DEC21C6A for ; Mon, 13 Mar 2017 13:06:23 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4mrB006694; Mon, 13 Mar 2017 08:04:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410288; bh=yVOmFqGmgaNT0PMEWDpiU4IJwah/imJ+Gs3l0ezTM0s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mPyq067L1o3QGCv50LuNmGhIEsfkmJcdmT5ljADamkKy2sU5l6HZwh0ttRcvW7aKX 9p+fUIlELtPt7WzHMphqr1dkxpfwercWbWZexLa4n/uZ3XtmlGZYF+RIA0FVjm7pae gQDqkO9MqapJgQaAliPKrpWRKCTvtzUrSSldhxJE= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4hdu031049; Mon, 13 Mar 2017 08:04:43 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:42 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjM003968; Mon, 13 Mar 2017 08:04:41 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:26 +0200 Message-ID: <1489410273-10159-4-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Franklin S Cooper Jr Subject: [U-Boot] [u-boot PATCH v4 03/10] ti_armv7_keystone2: Define scratch space in SRAM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Franklin S Cooper Jr Scratch space can be used for features such as board detection. Define an area within SRAM that can be used for this purpose. [rogerq@ti.com] Rename EEPROM macro Signed-off-by: Franklin S Cooper Jr Signed-off-by: Roger Quadros --- include/configs/ti_armv7_keystone2.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 5d4ef58..f76e0a5 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -55,6 +55,13 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +/* SRAM scratch space entries */ +#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 + +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) + /* UART Configuration */ #define CONFIG_SYS_NS16550_MEM32 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)