From patchwork Mon Mar 13 13:43:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95234 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1178250qgd; Mon, 13 Mar 2017 06:45:39 -0700 (PDT) X-Received: by 10.99.137.66 with SMTP id v63mr35881209pgd.207.1489412739281; Mon, 13 Mar 2017 06:45:39 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 38si510067pld.335.2017.03.13.06.45.39; Mon, 13 Mar 2017 06:45:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751958AbdCMNpe (ORCPT + 4 others); Mon, 13 Mar 2017 09:45:34 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:64699 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753246AbdCMNpL (ORCPT ); Mon, 13 Mar 2017 09:45:11 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DDhoWG012122; Mon, 13 Mar 2017 08:43:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489412630; bh=fwBOwky2RmKO4hMSG+sDlLgnHCfs4FtMmiufmowvHFE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PfPOSmAbA6bCxV74IFN7lQia9WPTwWq3jeJaGbRlMwYX7Zsu87IclLKVPw5d9iJ9U jdB+5AaDqVGuTJmfTuf3LUBFneTzK/tCsl1j7TSKh1FGDOcNiSS7zcoJUJztOzdTEt iJPodRK/S0pg+tOYYrMzCF4PsW2fnqjDsSWQV5ac= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhjQu019325; Mon, 13 Mar 2017 08:43:45 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:43:44 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhZvk017427; Mon, 13 Mar 2017 08:43:42 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , Niklas Cassel , , , , CC: , Subject: [PATCH v4 2/7] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops Date: Mon, 13 Mar 2017 19:13:23 +0530 Message-ID: <20170313134328.1588-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170313134328.1588-1-kishon@ti.com> References: <20170313134328.1588-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding cpu address. Acked-by: Joao Pinto Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 0984baff07e3..07c45ec07662 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -88,6 +88,11 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, writel(value, pcie->base + offset); } +static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr) +{ + return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; +} + static int dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); @@ -152,11 +157,6 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); - pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; - pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR; - dw_pcie_setup_rc(pp); dra7xx_pcie_establish_link(dra7xx); @@ -329,6 +329,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, } static const struct dw_pcie_ops dw_pcie_ops = { + .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, .link_up = dra7xx_pcie_link_up, };