From patchwork Mon Mar 20 13:11:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95531 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp936331qgd; Mon, 20 Mar 2017 06:15:58 -0700 (PDT) X-Received: by 10.36.36.142 with SMTP id f136mr10560351ita.0.1490015758209; Mon, 20 Mar 2017 06:15:58 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id x195si1935763itx.90.2017.03.20.06.15.57; Mon, 20 Mar 2017 06:15:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EDB6863E7F; Mon, 20 Mar 2017 13:15:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 55DA963E77; Mon, 20 Mar 2017 13:15:19 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9FA0A63E8B; Mon, 20 Mar 2017 13:15:16 +0000 (UTC) Received: from mail-pg0-f50.google.com (mail-pg0-f50.google.com [74.125.83.50]) by lists.linaro.org (Postfix) with ESMTPS id 76EDE63E74 for ; Mon, 20 Mar 2017 13:14:57 +0000 (UTC) Received: by mail-pg0-f50.google.com with SMTP id t143so11445116pgb.2 for ; Mon, 20 Mar 2017 06:14:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dZ+qAxsV8lgrVL8JOfxS0tv/oNfk9RG76x5ti1rk3o4=; b=sXLMKWYwrr7rCcq7Wlja5+Ppzp7osSUzH1OXkZ60t9GG7FoYsLKVvkBOL9d1u+Bl7P k3QnvwHylmDtAEiQEcAsVmz/J6cbpVbQnaOXWX6SzMYYTDiP8+J7sAf5hYe5ScKbPByx puHy0ZKgQMZWo1aNb0/4EciMvHPACC770C4D0U1Ft3J6ZLF/O5OHgJTVXEkUwfkAU4wF Sqnz7Wlz4ZZqld6000NX1W0fMmxu5tjGRvsO1DAEKCT2THD7O+9hf8qADfXS4snGbEe7 W2Rv98/D7um41Tu5JyuVknEl6NCU0/y9K2M2dANTI6yRn8sxmmXPNDu3aCXJaSYV1QfE tNGw== X-Gm-Message-State: AFeK/H0qC5DvJmH/y1VANOkZwjZ0wB5YugtNMDo8GhL+vACGxLfsFigR143NC4UFl8olAK0gqUXzYA== X-Received: by 10.84.128.75 with SMTP id 69mr5233316pla.111.1490015696720; Mon, 20 Mar 2017 06:14:56 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:14:56 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:07 +0800 Message-Id: <1490015485-53685-4-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 03/21] Hisilicon: disable RC Option Rom X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The M3(the corprocessor)PCIe driver will read Option Rom header durning enumeration, this opration will cause a completion error when there is no device inserted to the RC port, and the Option rom is uesless now. So we need to disable the RC Option Rom. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 3bad240..57699e0 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -904,6 +904,44 @@ void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) return; } +UINT32 SysRegRead(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg) +{ + UINT32 Value; + if (SocType == 0x1610) { + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value); + } else { + //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE + //in the same hostbridge. + RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value); + } + return Value; +} + +VOID +DisableRcOptionRom ( + UINT32 soctype, + UINT32 HostBridgeNum, + UINT32 Port, + PCIE_PORT_TYPE PcieType +) +{ + UINT32 Value = 0; + if (PcieType == PCIE_ROOT_COMPLEX) { + Value = SysRegRead(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value |= BIT2; //cs2 enable + SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + + Value = SysRegRead(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG); + Value &= ~BIT0; //disable option rom + SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value); + + Value = SysRegRead(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value &= ~BIT2; //cs2 disable + SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + } + return; +} + EFI_STATUS EFIAPI PciePortInit ( @@ -964,6 +1002,8 @@ PciePortInit ( /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); + /* Disable RC Option Rom */ + DisableRcOptionRom(soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) {