From patchwork Mon Mar 20 20:53:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 95586 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1131544qgd; Mon, 20 Mar 2017 13:53:22 -0700 (PDT) X-Received: by 10.98.160.84 with SMTP id r81mr35912289pfe.71.1490043202183; Mon, 20 Mar 2017 13:53:22 -0700 (PDT) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id r3si10419503pli.62.2017.03.20.13.53.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Mar 2017 13:53:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D01D480476; Mon, 20 Mar 2017 13:53:21 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x22f.google.com (mail-wm0-x22f.google.com [IPv6:2a00:1450:400c:c09::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0606180476 for ; Mon, 20 Mar 2017 13:53:20 -0700 (PDT) Received: by mail-wm0-x22f.google.com with SMTP id n11so74371083wma.0 for ; Mon, 20 Mar 2017 13:53:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RKM9Svb6dp6GzoqAImw8mNxfjhi5cIgUmvImlhdzGJ0=; b=IZOz8cS/z7vC1pXLWmPq1/6b4khBf1hD7utId5S1FoB8F4VIsG2gKrxQFBcYknmPcl wixFvDuIUJbz4XZR27rRDXxs6599MbI9pMA91T3jzvva60q0bfj9vWd7v4H5eQAaRfCp dHiBt2up/88GM1FUvZLHlR6gqFal6eBbvrnT8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RKM9Svb6dp6GzoqAImw8mNxfjhi5cIgUmvImlhdzGJ0=; b=BbG9uhmxMJ2tv0qOPq1xFOIam89zn/df+sVFCLo+0cyByPFET9va3KCGFkFbiuUgmB x4468UkI11sdPmMOqxREJFI0RHc1zUOp9z88Qt8O5g94RY1+lULT1mEx5MycyEanertb ndBj0RMxHsR4qX/WRKM46wwzRbrZOOQgjKhdcQaOMA5g4V8P/qKOJxc9ZRw8MOnNGqH0 dspfY8iv5xj6JwaH0m+pfsIc3uYqZu4wuT5yMWjxTyr+EY/aqlVQROjbUducJtAjCAQ5 vYo+kB80V2nmOfUsgAFIQRy02/v0WXfyALnucjsKkP3b844VlD/v541lVhhtJh8wYxQf hH/A== X-Gm-Message-State: AFeK/H1twpicGWeOwPJr9QtGBRLzUYGAPhF7KHTFRQcWLGiXC96WqeLgXXqUJW8SVIF3dpdp X-Received: by 10.28.135.149 with SMTP id j143mr11704273wmd.19.1490043198560; Mon, 20 Mar 2017 13:53:18 -0700 (PDT) Received: from localhost.localdomain (189.17.90.92.rev.sfr.net. [92.90.17.189]) by smtp.gmail.com with ESMTPSA id q1sm12184651wra.65.2017.03.20.13.53.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 13:53:17 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Mon, 20 Mar 2017 20:53:01 +0000 Message-Id: <1490043181-20031-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490043181-20031-1-git-send-email-ard.biesheuvel@linaro.org> References: <1490043181-20031-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 3/3] ArmPkg/ArmExceptionLib: use EL0 stack for synchronous exceptions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.harkin@linaro.org, Ard Biesheuvel , eugene@hp.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" In order to be able to produce meaningful diagnostic output when taking synchronous exceptions that have been caused by corruption of the stack pointer, prepare the EL0 stack pointer and switch to it when handling the 'Sync exception using SPx' exception class. Other exception classes (of which we really only care about IrqSPx) are left functionally intact. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Note that some code has been moved around so that the macro doesn't grow too big to fit in a 128 byte slot, while keeping the code logically consistent. ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c | 17 +++- ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 86 ++++++++++++-------- ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 5 +- 3 files changed, 70 insertions(+), 38 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c index 3d6eb4974d74..bd307628af87 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c @@ -16,7 +16,7 @@ #include #include - +#include #include // for MAX_AARCH64_EXCEPTION UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION; @@ -25,11 +25,26 @@ EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT; UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64 +#define EL0_STACK_PAGES 2 + +VOID +RegisterEl0Stack ( + IN VOID *Stack + ); + RETURN_STATUS ArchVectorConfig( IN UINTN VectorBaseAddress ) { UINTN HcrReg; + UINT8 *Stack; + + Stack = AllocatePages (EL0_STACK_PAGES); + if (Stack == NULL) { + return RETURN_OUT_OF_RESOURCES; + } + + RegisterEl0Stack ((UINT8 *)Stack + EFI_PAGES_TO_SIZE (EL0_STACK_PAGES)); if (ArmReadCurrentEL() == AARCH64_EL2) { HcrReg = ArmReadHcr(); diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index ff1f5fc81316..ac426d72a150 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -100,6 +100,7 @@ GCC_ASM_EXPORT(ExceptionHandlersEnd) GCC_ASM_EXPORT(CommonCExceptionHandler) +GCC_ASM_EXPORT(RegisterEl0Stack) .text @@ -122,35 +123,41 @@ ASM_PFX(ExceptionHandlersStart): VECTOR_BASE(ExceptionHandlersStart) #endif - .macro ExceptionEntry, val + .macro ExceptionEntry, val, sp=SPx + .ifnc \sp, SPx + msr SPsel, xzr + .endif + // Move the stackpointer so we can reach our structure with the str instruction. sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - // Push some GP registers so we can record the exception context + // Push the GP registers so we can record the exception context stp x0, x1, [sp, #-GP_CONTEXT_SIZE]! stp x2, x3, [sp, #0x10] stp x4, x5, [sp, #0x20] stp x6, x7, [sp, #0x30] + stp x8, x9, [sp, #0x40] + stp x10, x11, [sp, #0x50] + stp x12, x13, [sp, #0x60] + stp x14, x15, [sp, #0x70] + stp x16, x17, [sp, #0x80] + stp x18, x19, [sp, #0x90] + stp x20, x21, [sp, #0xa0] + stp x22, x23, [sp, #0xb0] + stp x24, x25, [sp, #0xc0] + stp x26, x27, [sp, #0xd0] + stp x28, x29, [sp, #0xe0] + add x28, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - EL1_OR_EL2_OR_EL3(x1) -1:mrs x2, elr_el1 // Exception Link Register - mrs x3, spsr_el1 // Saved Processor Status Register 32bit - mrs x5, esr_el1 // EL1 Exception syndrome register 32bit - mrs x6, far_el1 // EL1 Fault Address Register - b 4f - -2:mrs x2, elr_el2 // Exception Link Register - mrs x3, spsr_el2 // Saved Processor Status Register 32bit - mrs x5, esr_el2 // EL2 Exception syndrome register 32bit - mrs x6, far_el2 // EL2 Fault Address Register - b 4f - -3:mrs x2, elr_el3 // Exception Link Register - mrs x3, spsr_el3 // Saved Processor Status Register 32bit - mrs x5, esr_el3 // EL3 Exception syndrome register 32bit - mrs x6, far_el3 // EL3 Fault Address Register + .ifnc \sp, SPx + msr SPsel, #1 // Switch back to read the SP value upon entry + mov x7, sp + msr SPsel, xzr + .else + mov x7, x28 // x28 contains the SP value upon entry + .endif -4:mrs x4, fpsr // Floating point Status Register 32bit + stp x30, x7, [sp, #0xf0] // Record the type of exception that occurred. mov x0, #\val @@ -189,7 +196,7 @@ ASM_PFX(SErrorSP0): // VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC) ASM_PFX(SynchronousExceptionSPx): - ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS + ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0 VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ) ASM_PFX(IrqSPx): @@ -248,20 +255,25 @@ ASM_PFX(ExceptionHandlersEnd): ASM_PFX(CommonExceptionEntry): - // Stack the remaining GP registers - stp x8, x9, [sp, #0x40] - stp x10, x11, [sp, #0x50] - stp x12, x13, [sp, #0x60] - stp x14, x15, [sp, #0x70] - stp x16, x17, [sp, #0x80] - stp x18, x19, [sp, #0x90] - stp x20, x21, [sp, #0xa0] - stp x22, x23, [sp, #0xb0] - stp x24, x25, [sp, #0xc0] - stp x26, x27, [sp, #0xd0] - stp x28, x29, [sp, #0xe0] - add x28, sp, #GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE - stp x30, x28, [sp, #0xf0] + EL1_OR_EL2_OR_EL3(x1) +1:mrs x2, elr_el1 // Exception Link Register + mrs x3, spsr_el1 // Saved Processor Status Register 32bit + mrs x5, esr_el1 // EL1 Exception syndrome register 32bit + mrs x6, far_el1 // EL1 Fault Address Register + b 4f + +2:mrs x2, elr_el2 // Exception Link Register + mrs x3, spsr_el2 // Saved Processor Status Register 32bit + mrs x5, esr_el2 // EL2 Exception syndrome register 32bit + mrs x6, far_el2 // EL2 Fault Address Register + b 4f + +3:mrs x2, elr_el3 // Exception Link Register + mrs x3, spsr_el3 // Saved Processor Status Register 32bit + mrs x5, esr_el3 // EL3 Exception syndrome register 32bit + mrs x6, far_el3 // EL3 Fault Address Register + +4:mrs x4, fpsr // Floating point Status Register 32bit // Save the SYS regs stp x2, x3, [x28, #-SYS_CONTEXT_SIZE]! @@ -368,3 +380,7 @@ ASM_PFX(CommonExceptionEntry): add sp, sp, #FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE eret + +ASM_PFX(RegisterEl0Stack): + msr sp_el0, x0 + ret diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf index 10d9ae0f4afc..cd9149cf76c6 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf @@ -53,10 +53,11 @@ [Packages] [LibraryClasses] ArmLib - DebugLib - DefaultExceptionHandlerLib BaseMemoryLib CacheMaintenanceLib + DebugLib + DefaultExceptionHandlerLib + MemoryAllocationLib [Pcd] gArmTokenSpaceGuid.PcdDebuggerExceptionSupport