From patchwork Wed Mar 22 02:03:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 95688 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp19582qgd; Tue, 21 Mar 2017 19:04:12 -0700 (PDT) X-Received: by 10.98.54.196 with SMTP id d187mr43799709pfa.33.1490148252223; Tue, 21 Mar 2017 19:04:12 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a125si23235384pgc.9.2017.03.21.19.04.11; Tue, 21 Mar 2017 19:04:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758549AbdCVCDp (ORCPT + 7 others); Tue, 21 Mar 2017 22:03:45 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:33668 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932656AbdCVCDa (ORCPT ); Tue, 21 Mar 2017 22:03:30 -0400 Received: by mail-oi0-f66.google.com with SMTP id a94so7664628oic.0 for ; Tue, 21 Mar 2017 19:03:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RPR8i+gXwZatW82AtT45SKWfjNZsmyxzFyX008Z0CMA=; b=Z/wC526H8qL7+n2FDL4//98AO1Sg/aFCrtnvbIcOIy7JlajE+8JNSFz3UZ8OQv4EiW M6fA0iGqiVf48y30sEQYjCVdgV38e8FUnRxWVAQtsgN2pp1Fuw7j7FgOChWy3nCxfE+7 nbSpZyT4D/T9Ly49nxI9S2LWeeyGTnMIJpfl6cyvV81aQxB2A/VYJuwlRXN1DGvdw1rY P2TUrYeroW7IRhR8bYq3CZCrf4X6s8Rlc8yhLW8bSZNP8fe3mEAV3mx2bCEh71HHTYZw EwmzvRlUrcmOWrRikOgk3cIg6UUkyKka0nk6FIZ15rkxfq0vRkqXnc5iAF+ErmwvDJSd idWw== X-Gm-Message-State: AFeK/H15qtKBWMWEv7sIZj0Pph18+98IyVxsGBCs4ef+kWpOi6Dk46fjZRK5VNFmzhK2GQ== X-Received: by 10.202.180.213 with SMTP id d204mr20913981oif.82.1490148208804; Tue, 21 Mar 2017 19:03:28 -0700 (PDT) Received: from rob-hp-laptop.herring.priv (66-90-148-125.dyn.grandenetworks.net. [66.90.148.125]) by smtp.googlemail.com with ESMTPSA id 62sm4574632ott.19.2017.03.21.19.03.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Mar 2017 19:03:28 -0700 (PDT) From: Rob Herring To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: arm@kernel.org, Michal Simek , =?utf-8?b?U8O2?= =?utf-8?q?ren_Brinkmann?= Subject: [PATCH 15/15] arm64: dts: xilinx: fix PCI bus dtc warnings Date: Tue, 21 Mar 2017 21:03:13 -0500 Message-Id: <20170322020313.24338-15-robh@kernel.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170322020313.24338-1-robh@kernel.org> References: <20170322020313.24338-1-robh@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring Cc: Michal Simek Cc: "Sören Brinkmann" --- Sub-arch maintainers, please apply to your trees unless arm-soc wants to take the whole lot. arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.10.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 54dc28351c8c..1a3f5e928bb9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -221,6 +221,7 @@ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,