From patchwork Sat Mar 25 16:18:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Semwal X-Patchwork-Id: 95982 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp532125qgd; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) X-Received: by 10.84.197.131 with SMTP id n3mr18362973pld.43.1490458752298; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si6723034pli.62.2017.03.25.09.19.12; Sat, 25 Mar 2017 09:19:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751339AbdCYQTM (ORCPT + 5 others); Sat, 25 Mar 2017 12:19:12 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:34808 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdCYQTL (ORCPT ); Sat, 25 Mar 2017 12:19:11 -0400 Received: by mail-pg0-f45.google.com with SMTP id 21so9212281pgg.1 for ; Sat, 25 Mar 2017 09:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ObiQCHNzvTtSBLtXsuBgnkHnMfoknUeSeJVAfQttlYg=; b=RPjTJuAi+nOfveSjVpS1T+5nETqiHsvOuMS03Lwkbcg59g50CNgg+w/u58Fn1iwI1h VeosrMja1cOpqmV5MWSKVddQ01U3s8XRB/aYqE7dZNlNjDI0FxHcsWrtDwcDF/JYflTE PfCfXK8BcMOSrbc2MRequ1SKI/VM9UkCELrtY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ObiQCHNzvTtSBLtXsuBgnkHnMfoknUeSeJVAfQttlYg=; b=c9p4isi+iw261VziatknHfdlZ2zkuAxOvfk3LtMZuuF7hunCcDqJlOHCC9gc3AnvTG JHXwFW402vc3jeDi6AWkh8TNSIIrBCMHzSq14jiAM4JaHp0U4WrzGsG2J+46INyH7lXs MtvHVE/08pdSxOpMIVhraPoRCVjJZ/burJZQp5LNpWSAYWmUpzwnfN//IkUjFMq8wY// q3i7Y42CAHkN2z5v42eVHJr2su6ORdZd0DBImF4U008dTuKVwPHSiie7/E8uKfrcmhLK 3vGaf1MijRr7acnfaFAjeEX7O0qfL5+lr7gX3b1s9EGFQMSEyox/+S+BEiXs1JvqggmV gkWQ== X-Gm-Message-State: AFeK/H2ANenSLUJgKwt0DJ+MPdd5ua26Qo1o8r4BbQ4ttKOA08FhLG0CcWlLszA1IpCZA7if X-Received: by 10.84.238.22 with SMTP id u22mr18544748plk.137.1490458750052; Sat, 25 Mar 2017 09:19:10 -0700 (PDT) Received: from phantom.lan ([106.51.225.38]) by smtp.gmail.com with ESMTPSA id q194sm11469541pfq.43.2017.03.25.09.19.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 25 Mar 2017 09:19:08 -0700 (PDT) From: Sumit Semwal To: stable@vger.kernel.org Cc: Bjorn Helgaas , Sasha Levin , Greg Kroah-Hartman , Sumit Semwal Subject: [PATCH for-4.4 05/19] PCI: Separate VF BAR updates from standard BAR updates Date: Sat, 25 Mar 2017 21:48:05 +0530 Message-Id: <1490458699-24484-6-git-send-email-sumit.semwal@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> References: <1490458699-24484-1-git-send-email-sumit.semwal@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bjorn Helgaas [ Upstream commit 6ffa2489c51da77564a0881a73765ea2169f955d ] Previously pci_update_resource() used the same code path for updating standard BARs and VF BARs in SR-IOV capabilities. Split the VF BAR update into a new pci_iov_update_resource() internal interface, which makes it simpler to compute the BAR address (we can get rid of pci_resource_bar() and pci_iov_resource_bar()). This patch: - Renames pci_update_resource() to pci_std_update_resource(), - Adds pci_iov_update_resource(), - Makes pci_update_resource() a wrapper that calls the appropriate one, No functional change intended. Signed-off-by: Bjorn Helgaas Reviewed-by: Gavin Shan Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sumit Semwal --- drivers/pci/iov.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 1 + drivers/pci/setup-res.c | 13 +++++++++++-- 3 files changed, 62 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 31f31d4..a6b1001 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -572,6 +572,56 @@ int pci_iov_resource_bar(struct pci_dev *dev, int resno) 4 * (resno - PCI_IOV_RESOURCES); } +/** + * pci_iov_update_resource - update a VF BAR + * @dev: the PCI device + * @resno: the resource number + * + * Update a VF BAR in the SR-IOV capability of a PF. + */ +void pci_iov_update_resource(struct pci_dev *dev, int resno) +{ + struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL; + struct resource *res = dev->resource + resno; + int vf_bar = resno - PCI_IOV_RESOURCES; + struct pci_bus_region region; + u32 new; + int reg; + + /* + * The generic pci_restore_bars() path calls this for all devices, + * including VFs and non-SR-IOV devices. If this is not a PF, we + * have nothing to do. + */ + if (!iov) + return; + + /* + * Ignore unimplemented BARs, unused resource slots for 64-bit + * BARs, and non-movable resources, e.g., those described via + * Enhanced Allocation. + */ + if (!res->flags) + return; + + if (res->flags & IORESOURCE_UNSET) + return; + + if (res->flags & IORESOURCE_PCI_FIXED) + return; + + pcibios_resource_to_bus(dev->bus, ®ion, res); + new = region.start; + new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; + + reg = iov->pos + PCI_SRIOV_BAR + 4 * vf_bar; + pci_write_config_dword(dev, reg, new); + if (res->flags & IORESOURCE_MEM_64) { + new = region.start >> 16 >> 16; + pci_write_config_dword(dev, reg + 4, new); + } +} + resource_size_t __weak pcibios_iov_resource_alignment(struct pci_dev *dev, int resno) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index d390fc1..eda77d1 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -277,6 +277,7 @@ static inline void pci_restore_ats_state(struct pci_dev *dev) int pci_iov_init(struct pci_dev *dev); void pci_iov_release(struct pci_dev *dev); int pci_iov_resource_bar(struct pci_dev *dev, int resno); +void pci_iov_update_resource(struct pci_dev *dev, int resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 604011e..ac58c56 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -25,8 +25,7 @@ #include #include "pci.h" - -void pci_update_resource(struct pci_dev *dev, int resno) +static void pci_std_update_resource(struct pci_dev *dev, int resno) { struct pci_bus_region region; bool disable; @@ -110,6 +109,16 @@ void pci_update_resource(struct pci_dev *dev, int resno) pci_write_config_word(dev, PCI_COMMAND, cmd); } +void pci_update_resource(struct pci_dev *dev, int resno) +{ + if (resno <= PCI_ROM_RESOURCE) + pci_std_update_resource(dev, resno); +#ifdef CONFIG_PCI_IOV + else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) + pci_iov_update_resource(dev, resno); +#endif +} + int pci_claim_resource(struct pci_dev *dev, int resource) { struct resource *res = &dev->resource[resource];