From patchwork Mon Mar 27 09:43:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 96033 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1141768qgd; Mon, 27 Mar 2017 02:44:59 -0700 (PDT) X-Received: by 10.99.117.11 with SMTP id q11mr23767454pgc.9.1490607899015; Mon, 27 Mar 2017 02:44:59 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k21si83158pgg.16.2017.03.27.02.44.58; Mon, 27 Mar 2017 02:44:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752459AbdC0Jo6 (ORCPT + 19 others); Mon, 27 Mar 2017 05:44:58 -0400 Received: from mail-wr0-f182.google.com ([209.85.128.182]:35280 "EHLO mail-wr0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752147AbdC0Jom (ORCPT ); Mon, 27 Mar 2017 05:44:42 -0400 Received: by mail-wr0-f182.google.com with SMTP id u1so47695255wra.2 for ; Mon, 27 Mar 2017 02:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ly+5sx4ymdF+dlMpePUwcp3cxCnw6zrmXw1Z3zEBov8=; b=W2jZtxZ/hq/P5L9JxUvE4yb2LfA9xKr4u9J6jETo11jVc6Fnp9H92EM8PQe+1XbQHf rhgOY/POrZnPF/Bh8MZFrgeA/Rsx0jA5ScUaiHcToI9mQpkg0VYOTdoVbBUPm4aDSX0L asEZ/yGADnP4dizwGOYt0ZwUXOi//ROtbysEE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ly+5sx4ymdF+dlMpePUwcp3cxCnw6zrmXw1Z3zEBov8=; b=VJumWzWK5WNs2uoDN3G6eIxvHmOqjg4zZ8i4SSx2pS7k8iIwPgbK+X+F7rwVN/bnPD 28qdzZZRK2pGWvGebUsgqp77O64LJKO4cIBGMlOuTtGi/SuIfE6vFH6dNE/ZOGk5f7Jk MXtkLFUa8/xJ7MJgLUsGHZbzbmxCOitxj9hwA+yECCqSW+LQiMhkMbgnjFNfiPP0MV7F hcSUE/fJ91Qp4gZMQZjpoT2VW4kgAM8VTVwDB2l2qIiT95drU+LgfXx7EtMrUVAmmcUv SEGlpQ0dyPNYkrItP4/p7hk6pY1Ve9F6ZVfRfNDkBS7hej81Ioh1hUyUi1nLCaflWEoD BEiw== X-Gm-Message-State: AFeK/H0pJ+7smhtYEe2krYq+V2Oyt9rwtAsLo99+tL4f05rLfE4FLFhI+vXZy5lYqmVgesFB X-Received: by 10.28.157.140 with SMTP id g134mr9122194wme.81.1490607869232; Mon, 27 Mar 2017 02:44:29 -0700 (PDT) Received: from lmenx321.st.com. ([80.215.98.181]) by smtp.gmail.com with ESMTPSA id 36sm111583wrk.15.2017.03.27.02.44.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Mar 2017 02:44:28 -0700 (PDT) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: linux-kernel@vger.kernel.org, jic23@kernel.org, linux-iio@vger.kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, vilhelm.gray@gmail.com, mwelling@ieee.org Cc: fabrice.gasnier@st.com, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v3 2/2] iio: stm32 trigger: Add counter enable modes Date: Mon, 27 Mar 2017 11:43:24 +0200 Message-Id: <1490607804-24889-3-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490607804-24889-1-git-send-email-benjamin.gaignard@st.com> References: <1490607804-24889-1-git-send-email-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Device counting could be controlled by the level or the edges of a trigger. in_count0_enable_mode attibute allow to set the control mode. Signed-off-by: Benjamin Gaignard --- .../ABI/testing/sysfs-bus-iio-timer-stm32 | 23 +++++++ drivers/iio/trigger/stm32-timer-trigger.c | 70 ++++++++++++++++++++++ 2 files changed, 93 insertions(+) -- 1.9.1 Reviewed-by: William Breathitt Gray diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 index bf795ad..c0a1edc 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 @@ -59,3 +59,26 @@ Description: quadrature: Encoder A and B inputs are mixed to get direction and count with a scale of 0.25. + +What: /sys/bus/iio/devices/iio:deviceX/in_count_enable_mode_available +KernelVersion: 4.12 +Contact: benjamin.gaignard@st.com +Description: + Reading returns the list possible enable modes. + +What: /sys/bus/iio/devices/iio:deviceX/in_count0_enable_mode +KernelVersion: 4.12 +Contact: benjamin.gaignard@st.com +Description: + Configure the device counter enable modes, in all case + counting direction is set by in_count0_count_direction + attribute and the counter is clocked by the internal clock. + always: + Counter is always ON. + + gated: + Counting is enabled when connected trigger signal + level is high else counting is disabled. + + triggered: + Counting start on rising edge of the connected trigger. diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c index 7db904c..0f1a2cf 100644 --- a/drivers/iio/trigger/stm32-timer-trigger.c +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -353,6 +353,74 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev, .write_raw = stm32_counter_write_raw }; +static const char *const stm32_enable_modes[] = { + "always", + "gated", + "triggered", +}; + +static int stm32_enable_mode2sms(int mode) +{ + switch (mode) { + case 0: + return 0; + case 1: + return 5; + case 2: + return 6; + } + + return -EINVAL; +} + +static int stm32_set_enable_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + int sms = stm32_enable_mode2sms(mode); + + if (sms < 0) + return sms; + + regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); + + return 0; +} + +static int stm32_sms2enable_mode(int mode) +{ + switch (mode) { + case 0: + return 0; + case 5: + return 1; + case 6: + return 2; + } + + return -EINVAL; +} + +static int stm32_get_enable_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + u32 smcr; + + regmap_read(priv->regmap, TIM_SMCR, &smcr); + smcr &= TIM_SMCR_SMS; + + return stm32_sms2enable_mode(smcr); +} + +static const struct iio_enum stm32_enable_mode_enum = { + .items = stm32_enable_modes, + .num_items = ARRAY_SIZE(stm32_enable_modes), + .set = stm32_set_enable_mode, + .get = stm32_get_enable_mode +}; + static const char *const stm32_quadrature_modes[] = { "channel_A", "channel_B", @@ -466,6 +534,8 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum), IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum), IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum), + IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), + IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), {} };