| Message ID | 1490630670-15818-2-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg/sparc: zero extend ld/st helper args | expand |
Hi Peter, On 03/27/2017 01:04 PM, Peter Maydell wrote: > The C store helper functions take the data argument as a uint8_t, > uint16_t, etc depending on the store size. The SPARC calling > convention requires that data types smaller than the register > size must be extended by the caller. We weren't doing this, > which meant that if QEMU was compiled with optimizations enabled > we could end up storing incorrect values to guest memory. > (In particular the i386 guest BIOS would crash on startup.) > > Add code to the trampolines that call the store helpers to > do the zero extension as required. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > tcg/sparc/tcg-target.inc.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c > index d1f4c0d..548bea2 100644 > --- a/tcg/sparc/tcg-target.inc.c > +++ b/tcg/sparc/tcg-target.inc.c > @@ -843,6 +843,31 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) > static tcg_insn_unit *qemu_ld_trampoline[16]; > static tcg_insn_unit *qemu_st_trampoline[16]; > > +static void emit_extend(TCGContext *s, TCGReg r, int op) > +{ > + /* Emit zero extend of 8, 16 or 32 bit data as > + * required by the MO_* value op; do nothing for 64 bit. > + */ > + switch (op) { > + case MO_UB: > + tcg_out_arithi(s, r, r, 0xff, ARITH_AND); > + break; > + case MO_LEUW: > + case MO_BEUW: > + tcg_out_arithi(s, r, r, 16, SHIFT_SLL); > + tcg_out_arithi(s, r, r, 16, SHIFT_SRL); > + break; > + case MO_LEUL: > + case MO_BEUL: > + if (SPARC64) { > + tcg_out_arith(s, r, r, 0, SHIFT_SRL); > + } > + break; > + default: > + break; > + } it seems to me easier to read masking op: switch (op & MO_SIZE) { case MO_8: tcg_out_arithi(s, r, r, 0xff, ARITH_AND); break; case MO_16: tcg_out_arithi(s, r, r, 16, SHIFT_SLL); tcg_out_arithi(s, r, r, 16, SHIFT_SRL); break; case MO_32: if (SPARC64) { tcg_out_arith(s, r, r, 0, SHIFT_SRL); } break; case MO_64: break; } > +} > + > static void build_trampolines(TCGContext *s) > { > static void * const qemu_ld_helpers[16] = { > @@ -910,6 +935,7 @@ static void build_trampolines(TCGContext *s) > qemu_st_trampoline[i] = s->code_ptr; > > if (SPARC64) { > + emit_extend(s, TCG_REG_O2, i); shouldn't be inverting args? emit_extend(s, i, TCG_REG_O2); > ra = TCG_REG_O4; > } else { > ra = TCG_REG_O1; > @@ -925,6 +951,7 @@ static void build_trampolines(TCGContext *s) > tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); > ra += 2; > } else { > + emit_extend(s, i, ra); > ra += 1; > } > /* Skip the oi argument. */ > regards, Phil.
On 28 March 2017 at 16:52, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > On 03/27/2017 01:04 PM, Peter Maydell wrote: > it seems to me easier to read masking op: > > switch (op & MO_SIZE) { > case MO_8: > tcg_out_arithi(s, r, r, 0xff, ARITH_AND); > break; > case MO_16: > tcg_out_arithi(s, r, r, 16, SHIFT_SLL); > tcg_out_arithi(s, r, r, 16, SHIFT_SRL); > break; > case MO_32: > if (SPARC64) { > tcg_out_arith(s, r, r, 0, SHIFT_SRL); > } > break; > case MO_64: > break; > } Yes, agreed. >> +} >> + >> static void build_trampolines(TCGContext *s) >> { >> static void * const qemu_ld_helpers[16] = { >> @@ -910,6 +935,7 @@ static void build_trampolines(TCGContext *s) >> qemu_st_trampoline[i] = s->code_ptr; >> >> if (SPARC64) { >> + emit_extend(s, TCG_REG_O2, i); > > > shouldn't be inverting args? > emit_extend(s, i, TCG_REG_O2); emit_extend() takes the TCG reg first and the 'op' second, so this call is correct... >> ra = TCG_REG_O4; >> } else { >> ra = TCG_REG_O1; >> @@ -925,6 +951,7 @@ static void build_trampolines(TCGContext *s) >> tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); >> ra += 2; >> } else { >> + emit_extend(s, i, ra); ...but this one isn't; I don't have 32-bit sparc host to test with so I missed the error. >> ra += 1; >> } >> /* Skip the oi argument. */ thanks -- PMM
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index d1f4c0d..548bea2 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -843,6 +843,31 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) static tcg_insn_unit *qemu_ld_trampoline[16]; static tcg_insn_unit *qemu_st_trampoline[16]; +static void emit_extend(TCGContext *s, TCGReg r, int op) +{ + /* Emit zero extend of 8, 16 or 32 bit data as + * required by the MO_* value op; do nothing for 64 bit. + */ + switch (op) { + case MO_UB: + tcg_out_arithi(s, r, r, 0xff, ARITH_AND); + break; + case MO_LEUW: + case MO_BEUW: + tcg_out_arithi(s, r, r, 16, SHIFT_SLL); + tcg_out_arithi(s, r, r, 16, SHIFT_SRL); + break; + case MO_LEUL: + case MO_BEUL: + if (SPARC64) { + tcg_out_arith(s, r, r, 0, SHIFT_SRL); + } + break; + default: + break; + } +} + static void build_trampolines(TCGContext *s) { static void * const qemu_ld_helpers[16] = { @@ -910,6 +935,7 @@ static void build_trampolines(TCGContext *s) qemu_st_trampoline[i] = s->code_ptr; if (SPARC64) { + emit_extend(s, TCG_REG_O2, i); ra = TCG_REG_O4; } else { ra = TCG_REG_O1; @@ -925,6 +951,7 @@ static void build_trampolines(TCGContext *s) tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX); ra += 2; } else { + emit_extend(s, i, ra); ra += 1; } /* Skip the oi argument. */
The C store helper functions take the data argument as a uint8_t, uint16_t, etc depending on the store size. The SPARC calling convention requires that data types smaller than the register size must be extended by the caller. We weren't doing this, which meant that if QEMU was compiled with optimizations enabled we could end up storing incorrect values to guest memory. (In particular the i386 guest BIOS would crash on startup.) Add code to the trampolines that call the store helpers to do the zero extension as required. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tcg/sparc/tcg-target.inc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.7.4