[Linaro-uefi,Linaro-uefi,v2,02/17] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue.

Message ID 1491046162-53797-3-git-send-email-chenhui.sun@linaro.org
State Superseded
Headers show
Series
  • D03/D05 platforms bug fix
Related show

Commit Message

Chenhui Sun April 1, 2017, 11:29 a.m.
The I350 Hilink state is not stable, so we need to modify the
rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: shaochangliang <shaochangliang@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Signed-off-by: Chenhui Sun <chenhui.sun@linaro.org>
---
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++
 2 files changed, 6 insertions(+)

Comments

Leif Lindholm April 6, 2017, 4:32 p.m. | #1
On Sat, Apr 01, 2017 at 07:29:07PM +0800, Chenhui Sun wrote:
> The I350 Hilink state is not stable, so we need to modify the
> rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: shaochangliang <shaochangliang@huawei.com>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
> Signed-off-by: Chenhui Sun <chenhui.sun@linaro.org>
> ---
>  Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++
>  Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> index 0b5a659..be02044 100644
> --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> @@ -470,6 +470,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
>              RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
>              Value |= (1 << 20); //bit 20: rxvalid enable
>              RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
> +            RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \
> +              CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG);

Not addressed from previous feedback: spaces around '|'.

The rest looks fine now.

/
    Leif

>          }
>          PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
>          RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
> diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
> index 9671c57..9a0f636 100644
> --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
> +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
> @@ -70,6 +70,10 @@
>  
>  #define PCS_SDS_CFG_REG            0x204
>  #define SDS_CFG_STRIDE             0x4
> +#define MUX_LOS_ALOS_REG_OFFSET    0x508
> +#define MUX_CFG_STRIDE             0x4
> +#define CH_RXTX_STATUS_CFG_EN      BIT1
> +#define CH_RXTX_STATUS_CFG         BIT2
>  #define RegWrite(addr,data)            MmioWrite32((addr), (data))
>  #define RegRead(addr,data)             ((data) = MmioRead32 (addr))
>  
> -- 
> 1.9.1
>

Patch

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index 0b5a659..be02044 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -470,6 +470,8 @@  VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
             RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
             Value |= (1 << 20); //bit 20: rxvalid enable
             RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value);
+            RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \
+              CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG);
         }
         PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
         RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
index 9671c57..9a0f636 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h
@@ -70,6 +70,10 @@ 
 
 #define PCS_SDS_CFG_REG            0x204
 #define SDS_CFG_STRIDE             0x4
+#define MUX_LOS_ALOS_REG_OFFSET    0x508
+#define MUX_CFG_STRIDE             0x4
+#define CH_RXTX_STATUS_CFG_EN      BIT1
+#define CH_RXTX_STATUS_CFG         BIT2
 #define RegWrite(addr,data)            MmioWrite32((addr), (data))
 #define RegRead(addr,data)             ((data) = MmioRead32 (addr))