From patchwork Tue Apr 4 06:16:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96667 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp47912qgd; Mon, 3 Apr 2017 23:17:05 -0700 (PDT) X-Received: by 10.84.210.79 with SMTP id z73mr26255771plh.78.1491286625161; Mon, 03 Apr 2017 23:17:05 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m188si16434436pfc.145.2017.04.03.23.17.05; Mon, 03 Apr 2017 23:17:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752380AbdDDGRE (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:04 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:32814 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751046AbdDDGRD (ORCPT ); Tue, 4 Apr 2017 02:17:03 -0400 Received: by mail-pg0-f41.google.com with SMTP id x125so142531830pgb.0 for ; Mon, 03 Apr 2017 23:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bty6R6DYul67AKn+issoCh5QE2qoeZmvASm1stWPxWQ=; b=d01WXXFal1MfKSYlfe1VQzteZiKn9NAaIchn2t3AfRXDNcgZAzESaMwgT1yqlC1mUW AzYklgMnA/5/bhuDsx6WjWUMPRhHdn2/nYG941bM9/AGPTy1YroyisxBQUg9ux0KneeH e0v6b/pGnw1IulDjmXA28bL6ES/ewMD6frDUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bty6R6DYul67AKn+issoCh5QE2qoeZmvASm1stWPxWQ=; b=ojnAxBgX6hYusMd8otqI/clRrQ+e6hNEIMz5+8bS9ol7VP+K4KMiLt0tSDhYm2OiIC q6iHHyds3jLcwgLrMO5ae1HnKfwyqll25PkmepaIeyGnPRW5lUf1qzQ8sCdrrzoX1792 maHrLIfKiOSuO+jTzxXkMBU8HivFK9AC6jX0w1xGeFV4ALeg7aQ4UtoDmlMbEv4701rt Q36fBTguOzjm1z9rE/LhvcfJ93+8DpIfxh7plU+KjS/ufBRkjonmHq0mDXTGUh6SIpt3 j1nlz33bIIibxenTLQviZact6CR7BAdtSJmljgWrjl0+YYIxPFmYpYJuEbU0AS4UJ+tK t2Hg== X-Gm-Message-State: AFeK/H2pa8wonq+YKrRTtEJsHCBKzRhuqEH8VX1xE1MyRRbco3gnPu9ZElv3QWbpXS63YodP X-Received: by 10.98.138.80 with SMTP id y77mr292303pfd.183.1491286623035; Mon, 03 Apr 2017 23:17:03 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id f81sm29247068pfe.61.2017.04.03.23.17.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:02 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Felix Fietkau , linux-mips@linux-mips.org, James Hogan Subject: [PATCH 05/33] MIPS: Lantiq: Fix cascaded IRQ setup Date: Tue, 4 Apr 2017 11:46:53 +0530 Message-Id: <1491286617-31131-2-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286617-31131-1-git-send-email-amit.pundir@linaro.org> References: <1491286617-31131-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Felix Fietkau With the IRQ stack changes integrated, the XRX200 devices started emitting a constant stream of kernel messages like this: [ 565.415310] Spurious IRQ: CAUSE=0x1100c300 This is caused by IP0 getting handled by plat_irq_dispatch() rather than its vectored interrupt handler, which is fixed by commit de856416e714 ("MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch"). Fix plat_irq_dispatch() to handle non-vectored IPI interrupts correctly by setting up IP2-6 as proper chained IRQ handlers and calling do_IRQ for all MIPS CPU interrupts. Signed-off-by: Felix Fietkau Acked-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15077/ [james.hogan@imgtec.com: tweaked commit message] Signed-off-by: James Hogan (cherry picked from commit 6c356eda225e3ee134ed4176b9ae3a76f793f4dd) Signed-off-by: Amit Pundir --- arch/mips/lantiq/irq.c | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c index 8ac0e59..0ddf369 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -269,6 +269,11 @@ static void ltq_hw5_irqdispatch(void) DEFINE_HWx_IRQDISPATCH(5) #endif +static void ltq_hw_irq_handler(struct irq_desc *desc) +{ + ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); +} + #ifdef CONFIG_MIPS_MT_SMP void __init arch_init_ipiirq(int irq, struct irqaction *action) { @@ -313,23 +318,19 @@ static struct irqaction irq_call = { asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - unsigned int i; - - if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - for (i = 0; i < MAX_IM; i++) { - if (pending & (CAUSEF_IP2 << i)) { - ltq_hw_irqdispatch(i); - goto out; - } - } + int irq; + + if (!pending) { + spurious_interrupt(); + return; } - pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); -out: - return; + pending >>= CAUSEB_IP; + while (pending) { + irq = fls(pending) - 1; + do_IRQ(MIPS_CPU_IRQ_BASE + irq); + pending &= ~BIT(irq); + } } static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) @@ -354,11 +355,6 @@ static const struct irq_domain_ops irq_domain_ops = { .map = icu_map, }; -static struct irqaction cascade = { - .handler = no_action, - .name = "cascade", -}; - int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; @@ -390,7 +386,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) mips_cpu_irq_init(); for (i = 0; i < MAX_IM; i++) - setup_irq(i + 2, &cascade); + irq_set_chained_handler(i + 2, ltq_hw_irq_handler); if (cpu_has_vint) { pr_info("Setting up vectored interrupts\n");