@@ -1,434 +1,432 @@
-/*
- * DTS file for AMD Seattle (Rev.B) Overdrive Development Board
- *
- * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
- *
- * This program and the accompanying materials are licensed and made available
- * under the terms and conditions of the BSD License which accompanies this
- * distribution. The full text of the license may be found at
- * http://opensource.org/licenses/bsd-license.php
- *
- * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
- * IMPLIED.
- *
- */
-
-/dts-v1/;
-
-/ {
- model = "AMD Seattle (Rev.B) Development Board (Overdrive)";
- compatible = "amd,seattle-overdrive", "amd,seattle";
- interrupt-parent = <0x1>;
- #address-cells = <0x2>;
- #size-cells = <0x2>;
-
- interrupt-controller@e1101000 {
- compatible = "arm,gic-400", "arm,cortex-a15-gic";
- interrupt-controller;
- #interrupt-cells = <0x3>;
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- reg = <0x0 0xe1110000 0x0 0x1000>,
- <0x0 0xe112f000 0x0 0x2000>,
- <0x0 0xe1140000 0x0 0x10000>,
- <0x0 0xe1160000 0x0 0x10000>;
- interrupts = <0x1 0x9 0xf04>;
- ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
- linux,phandle = <0x1>;
- phandle = <0x1>;
-
- v2m@e0080000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x0 0x80000 0x0 0x1000>;
- linux,phandle = <0x4>;
- phandle = <0x4>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <0x1 0xd 0xff04>,
- <0x1 0xe 0xff04>,
- <0x1 0xb 0xff04>,
- <0x1 0xa 0xff04>;
- };
-
- smb {
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
- /*
- * dma-ranges is 40-bit address space containing:
- * - GICv2m MSI register is at 0xe0080000
- * - DRAM range [0x8000000000 to 0xffffffffff]
- */
- dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
-
- clk100mhz_0 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <100000000>;
- clock-output-names = "adl3clk_100mhz";
- };
-
- clk375mhz {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <375000000>;
- clock-output-names = "ccpclk_375mhz";
- };
-
- clk333mhz {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <333000000>;
- clock-output-names = "sataclk_333mhz";
- linux,phandle = <0x2>;
- phandle = <0x2>;
- };
-
- clk500mhz_0 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <500000000>;
- clock-output-names = "pcieclk_500mhz";
- };
-
- clk500mhz_1 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <500000000>;
- clock-output-names = "dmaclk_500mhz";
- };
-
- clk250mhz_4 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <250000000>;
- clock-output-names = "miscclk_250mhz";
- linux,phandle = <0xd>;
- phandle = <0xd>;
- };
-
- clk100mhz_1 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <100000000>;
- clock-output-names = "uartspiclk_100mhz";
- linux,phandle = <0x3>;
- phandle = <0x3>;
- };
-
- sata@e0300000 {
- compatible = "snps,dwc-ahci";
- reg = <0x0 0xe0300000 0x0 0xf0000>;
- interrupts = <0x0 0x163 0x4>;
- clocks = <0x2>;
- dma-coherent;
- };
-
- sata@e0d00000 {
- status = "disabled";
- compatible = "snps,dwc-ahci";
- reg = <0x0 0xe0d00000 0x0 0xf0000>;
- interrupts = <0x0 0x162 0x4>;
- clocks = <0x2>;
- dma-coherent;
- };
-
- i2c@e1000000 {
- compatible = "snps,designware-i2c";
- reg = <0x0 0xe1000000 0x0 0x1000>;
- interrupts = <0x0 0x165 0x4>;
- clocks = <0xd>;
- };
-
- i2c@e0050000 {
- compatible = "snps,designware-i2c";
- reg = <0x0 0xe0050000 0x0 0x1000>;
- interrupts = <0x0 0x154 0x4>;
- clocks = <0xd>;
- };
-
- serial@e1010000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xe1010000 0x0 0x1000>;
- interrupts = <0x0 0x148 0x4>;
- clocks = <0x3 0x3>;
- clock-names = "uartclk", "apb_pclk";
- };
-
- ssp@e1020000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xe1020000 0x0 0x1000>;
- spi-controller;
- interrupts = <0x0 0x14a 0x4>;
- clocks = <0x3>;
- clock-names = "apb_pclk";
- };
-
- ssp@e1030000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x0 0xe1030000 0x0 0x1000>;
- spi-controller;
- interrupts = <0x0 0x149 0x4>;
- clocks = <0x3>;
- clock-names = "apb_pclk";
- num-cs = <0x1>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
-
- sdcard@0 {
- compatible = "mmc-spi-slot";
- reg = <0x0>;
- spi-max-frequency = <20000000>;
- voltage-ranges = <3200 3400>;
- pl022,hierarchy = <0x0>;
- pl022,interface = <0x0>;
- pl022,com-mode = <0x0>;
- pl022,rx-level-trig = <0x0>;
- pl022,tx-level-trig = <0x0>;
- };
- };
-
- gpio@e1050000 { /* [0 : 7] */
- compatible = "arm,pl061", "arm,primecell";
- #gpio-cells = <0x2>;
- reg = <0x0 0xe1050000 0x0 0x1000>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- interrupts = <0x0 0x166 0x4>;
- clocks = <0x3>;
- clock-names = "apb_pclk";
- };
-
- gpio@e0020000 { /* [8 : 15] */
- status = "disabled";
- compatible = "arm,pl061", "arm,primecell";
- #gpio-cells = <0x2>;
- reg = <0x0 0xe0020000 0x0 0x1000>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- interrupts = <0x0 0x16e 0x4>;
- clocks = <0x3>;
- clock-names = "apb_pclk";
- };
-
- gpio@e0030000 { /* [16 : 23] */
- status = "disabled";
- compatible = "arm,pl061", "arm,primecell";
- #gpio-cells = <0x2>;
- reg = <0x0 0xe0030000 0x0 0x1000>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- interrupts = <0x0 0x16d 0x4>;
- clocks = <0x3>;
- clock-names = "apb_pclk";
- };
-
- gpio@e0080000 { /* [24] */
- compatible = "arm,pl061", "arm,primecell";
- #gpio-cells = <0x2>;
- reg = <0x0 0xe0080000 0x0 0x1000>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- interrupts = <0x0 0x169 0x4>;
- clocks = <0x3>;
- clock-names = "apb_pclk";
- };
-
- ccp: ccp@e0100000 {
- compatible = "amd,ccp-seattle-v1a";
- reg = <0x0 0xe0100000 0x0 0x10000>;
- interrupts = <0x0 0x3 0x4>;
- dma-coherent;
- amd,zlib-support = <0x1>;
- };
-
- pcie: pcie@f0000000 {
- compatible = "pci-host-ecam-generic";
- #address-cells = <0x3>;
- #size-cells = <0x2>;
- #interrupt-cells = <0x1>;
- device_type = "pci";
- bus-range = <0x0 0x7f>;
- msi-parent = <0x4>;
- reg = <0x0 0xf0000000 0x0 0x10000000>;
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
- <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
- <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
- <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>;
- dma-coherent;
- dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
- ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
- <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
- <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
- };
-
- ccn@0xe8000000 {
- compatible = "arm,ccn-504";
- reg = <0x0 0xe8000000 0x0 0x1000000>;
- interrupts = <0x0 0x17c 0x4>;
- };
-
- gwdt@e0bb0000 {
- status = "disabled";
- compatible = "arm,sbsa-gwdt";
- reg = <0x0 0xe0bb0000 0x0 0x10000
- 0x0 0xe0bc0000 0x0 0x10000>;
- reg-names = "refresh", "control";
- interrupts = <0x0 0x151 0x4>;
- interrupt-names = "ws0";
- };
-
- kcs@e0010000 {
- status = "disabled";
- compatible = "ipmi-kcs";
- device_type = "ipmi";
- reg = <0x0 0xe0010000 0 0x8>;
- interrupts = <0 389 4>;
- interrupt-names = "ipmi_kcs";
- reg-size = <1>;
- reg-spacing = <4>;
- };
-
- clk250mhz_0 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <250000000>;
- clock-output-names = "xgmacclk0_dma_250mhz";
- linux,phandle = <0x5>;
- phandle = <0x5>;
- };
-
- clk250mhz_1 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <250000000>;
- clock-output-names = "xgmacclk0_ptp_250mhz";
- linux,phandle = <0x6>;
- phandle = <0x6>;
- };
-
- clk250mhz_2 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <250000000>;
- clock-output-names = "xgmacclk1_dma_250mhz";
- linux,phandle = <0x7>;
- phandle = <0x7>;
- };
-
- clk250mhz_3 {
- compatible = "fixed-clock";
- #clock-cells = <0x0>;
- clock-frequency = <250000000>;
- clock-output-names = "xgmacclk1_ptp_250mhz";
- linux,phandle = <0x8>;
- phandle = <0x8>;
- };
-
- phy@e1240800 {
- status = "disabled";
- compatible = "amd,xgbe-phy-seattle-v1a";
- reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
- <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
- <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
- interrupts = <0x0 0x143 0x4>;
- amd,speed-set = <0x0>;
- amd,serdes-blwc = <0x1 0x1 0x0>;
- amd,serdes-cdr-rate = <0x2 0x2 0x7>;
- amd,serdes-pq-skew = <0xa 0xa 0x12>;
- amd,serdes-tx-amp = <0xf 0xf 0xa>;
- amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
- amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
- linux,phandle = <0x9>;
- phandle = <0x9>;
- };
-
- phy@e1240c00 {
- status = "disabled";
- compatible = "amd,xgbe-phy-seattle-v1a";
- reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
- <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
- <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
- interrupts = <0x0 0x142 0x4>;
- amd,speed-set = <0x0>;
- amd,serdes-blwc = <0x1 0x1 0x0>;
- amd,serdes-cdr-rate = <0x2 0x2 0x7>;
- amd,serdes-pq-skew = <0xa 0xa 0x12>;
- amd,serdes-tx-amp = <0xf 0xf 0xa>;
- amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
- amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
- linux,phandle = <0xa>;
- phandle = <0xa>;
- };
-
- xgmac@e0700000 {
- status = "disabled";
- compatible = "amd,xgbe-seattle-v1a";
- reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
- interrupts = <0x0 0x145 0x4>,
- <0x0 0x15a 0x1>,
- <0x0 0x15b 0x1>,
- <0x0 0x15c 0x1>,
- <0x0 0x15d 0x1>;
- amd,per-channel-interrupt;
- mac-address = [02 a1 a2 a3 a4 a5];
- clocks = <0x5 0x6>;
- clock-names = "dma_clk", "ptp_clk";
- phy-handle = <0x9>;
- phy-mode = "xgmii";
- #stream-id-cells = <0x18>;
- dma-coherent;
- linux,phandle = <0xb>;
- phandle = <0xb>;
- };
-
- xgmac@e0900000 {
- status = "disabled";
- compatible = "amd,xgbe-seattle-v1a";
- reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
- interrupts = <0x0 0x144 0x4>,
- <0x0 0x155 0x1>,
- <0x0 0x156 0x1>,
- <0x0 0x157 0x1>,
- <0x0 0x158 0x1>;
- amd,per-channel-interrupt;
- mac-address = [02 b1 b2 b3 b4 b5];
- clocks = <0x7 0x8>;
- clock-names = "dma_clk", "ptp_clk";
- phy-handle = <0xa>;
- phy-mode = "xgmii";
- #stream-id-cells = <0x18>;
- dma-coherent;
- linux,phandle = <0xc>;
- phandle = <0xc>;
- };
- };
-
- chosen {
- stdout-path = "/smb/serial@e1010000";
- /* Note:
- * Linux support for pci-probe-only DT is not
- * stable. Disable this for now and let Linux
- * take care of the resource assignment.
- */
- // linux,pci-probe-only;
- };
-
- psci {
- compatible = "arm,psci-0.2", "arm,psci";
- method = "smc";
- };
-};
-
-
+/*
+ * DTS file for AMD Seattle (Rev.B) Overdrive Development Board
+ *
+ * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * This program and the accompanying materials are licensed and made available
+ * under the terms and conditions of the BSD License which accompanies this
+ * distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "AMD Seattle (Rev.B) Development Board (Overdrive)";
+ compatible = "amd,seattle-overdrive", "amd,seattle";
+ interrupt-parent = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ interrupt-controller@e1101000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ reg = <0x0 0xe1110000 0x0 0x1000>,
+ <0x0 0xe112f000 0x0 0x2000>,
+ <0x0 0xe1140000 0x0 0x10000>,
+ <0x0 0xe1160000 0x0 0x10000>;
+ interrupts = <0x1 0x9 0xf04>;
+ ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
+ linux,phandle = <0x1>;
+ phandle = <0x1>;
+
+ v2m@e0080000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0x80000 0x0 0x1000>;
+ linux,phandle = <0x4>;
+ phandle = <0x4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 0xd 0xff04>,
+ <0x1 0xe 0xff04>,
+ <0x1 0xb 0xff04>,
+ <0x1 0xa 0xff04>;
+ };
+
+ smb {
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ /*
+ * dma-ranges is 40-bit address space containing:
+ * - GICv2m MSI register is at 0xe0080000
+ * - DRAM range [0x8000000000 to 0xffffffffff]
+ */
+ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+
+ clk100mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "adl3clk_100mhz";
+ };
+
+ clk375mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <375000000>;
+ clock-output-names = "ccpclk_375mhz";
+ };
+
+ clk333mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <333000000>;
+ clock-output-names = "sataclk_333mhz";
+ linux,phandle = <0x2>;
+ phandle = <0x2>;
+ };
+
+ clk500mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "pcieclk_500mhz";
+ };
+
+ clk500mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <500000000>;
+ clock-output-names = "dmaclk_500mhz";
+ };
+
+ clk250mhz_4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "miscclk_250mhz";
+ linux,phandle = <0xd>;
+ phandle = <0xd>;
+ };
+
+ clk100mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "uartspiclk_100mhz";
+ linux,phandle = <0x3>;
+ phandle = <0x3>;
+ };
+
+ sata@e0300000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x0 0xe0300000 0x0 0xf0000>;
+ interrupts = <0x0 0x163 0x4>;
+ clocks = <0x2>;
+ dma-coherent;
+ };
+
+ sata@e0d00000 {
+ status = "disabled";
+ compatible = "snps,dwc-ahci";
+ reg = <0x0 0xe0d00000 0x0 0xf0000>;
+ interrupts = <0x0 0x162 0x4>;
+ clocks = <0x2>;
+ dma-coherent;
+ };
+
+ i2c@e1000000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xe1000000 0x0 0x1000>;
+ interrupts = <0x0 0x165 0x4>;
+ clocks = <0xd>;
+ };
+
+ i2c@e0050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xe0050000 0x0 0x1000>;
+ interrupts = <0x0 0x154 0x4>;
+ clocks = <0xd>;
+ };
+
+ serial@e1010000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xe1010000 0x0 0x1000>;
+ interrupts = <0x0 0x148 0x4>;
+ clocks = <0x3 0x3>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ ssp@e1020000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xe1020000 0x0 0x1000>;
+ spi-controller;
+ interrupts = <0x0 0x14a 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ ssp@e1030000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xe1030000 0x0 0x1000>;
+ spi-controller;
+ interrupts = <0x0 0x149 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ num-cs = <0x1>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ sdcard@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3200 3400>;
+ pl022,hierarchy = <0x0>;
+ pl022,interface = <0x0>;
+ pl022,com-mode = <0x0>;
+ pl022,rx-level-trig = <0x0>;
+ pl022,tx-level-trig = <0x0>;
+ };
+ };
+
+ gpio@e1050000 { /* [0 : 7] */
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe1050000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x166 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0020000 { /* [8 : 15] */
+ status = "disabled";
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0020000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x16e 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0030000 { /* [16 : 23] */
+ status = "disabled";
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0030000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x16d 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio@e0080000 { /* [24] */
+ compatible = "arm,pl061", "arm,primecell";
+ #gpio-cells = <0x2>;
+ reg = <0x0 0xe0080000 0x0 0x1000>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ interrupts = <0x0 0x169 0x4>;
+ clocks = <0x3>;
+ clock-names = "apb_pclk";
+ };
+
+ ccp: ccp@e0100000 {
+ compatible = "amd,ccp-seattle-v1a";
+ reg = <0x0 0xe0100000 0x0 0x10000>;
+ interrupts = <0x0 0x3 0x4>;
+ dma-coherent;
+ amd,zlib-support = <0x1>;
+ };
+
+ pcie: pcie@f0000000 {
+ compatible = "pci-host-ecam-generic";
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ #interrupt-cells = <0x1>;
+ device_type = "pci";
+ bus-range = <0x0 0x7f>;
+ msi-parent = <0x4>;
+ reg = <0x0 0xf0000000 0x0 0x10000000>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>,
+ <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>,
+ <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>,
+ <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>;
+ dma-coherent;
+ dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
+ ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
+ <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
+ <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
+ };
+
+ ccn@0xe8000000 {
+ compatible = "arm,ccn-504";
+ reg = <0x0 0xe8000000 0x0 0x1000000>;
+ interrupts = <0x0 0x17c 0x4>;
+ };
+
+ gwdt@e0bb0000 {
+ status = "disabled";
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0xe0bb0000 0x0 0x10000
+ 0x0 0xe0bc0000 0x0 0x10000>;
+ reg-names = "refresh", "control";
+ interrupts = <0x0 0x151 0x4>;
+ interrupt-names = "ws0";
+ };
+
+ kcs@e0010000 {
+ status = "disabled";
+ compatible = "ipmi-kcs";
+ device_type = "ipmi";
+ reg = <0x0 0xe0010000 0 0x8>;
+ interrupts = <0 389 4>;
+ interrupt-names = "ipmi_kcs";
+ reg-size = <1>;
+ reg-spacing = <4>;
+ };
+
+ clk250mhz_0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk0_dma_250mhz";
+ linux,phandle = <0x5>;
+ phandle = <0x5>;
+ };
+
+ clk250mhz_1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk0_ptp_250mhz";
+ linux,phandle = <0x6>;
+ phandle = <0x6>;
+ };
+
+ clk250mhz_2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk1_dma_250mhz";
+ linux,phandle = <0x7>;
+ phandle = <0x7>;
+ };
+
+ clk250mhz_3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <250000000>;
+ clock-output-names = "xgmacclk1_ptp_250mhz";
+ linux,phandle = <0x8>;
+ phandle = <0x8>;
+ };
+
+ phy@e1240800 {
+ status = "disabled";
+ compatible = "amd,xgbe-phy-seattle-v1a";
+ reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
+ <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
+ <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
+ interrupts = <0x0 0x143 0x4>;
+ amd,speed-set = <0x0>;
+ amd,serdes-blwc = <0x1 0x1 0x0>;
+ amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+ amd,serdes-pq-skew = <0xa 0xa 0x12>;
+ amd,serdes-tx-amp = <0xf 0xf 0xa>;
+ amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+ amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+ linux,phandle = <0x9>;
+ phandle = <0x9>;
+ };
+
+ phy@e1240c00 {
+ status = "disabled";
+ compatible = "amd,xgbe-phy-seattle-v1a";
+ reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
+ <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
+ <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
+ interrupts = <0x0 0x142 0x4>;
+ amd,speed-set = <0x0>;
+ amd,serdes-blwc = <0x1 0x1 0x0>;
+ amd,serdes-cdr-rate = <0x2 0x2 0x7>;
+ amd,serdes-pq-skew = <0xa 0xa 0x12>;
+ amd,serdes-tx-amp = <0xf 0xf 0xa>;
+ amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
+ amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
+ linux,phandle = <0xa>;
+ phandle = <0xa>;
+ };
+
+ xgmac@e0700000 {
+ status = "disabled";
+ compatible = "amd,xgbe-seattle-v1a";
+ reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
+ interrupts = <0x0 0x145 0x4>,
+ <0x0 0x15a 0x1>,
+ <0x0 0x15b 0x1>,
+ <0x0 0x15c 0x1>,
+ <0x0 0x15d 0x1>;
+ amd,per-channel-interrupt;
+ mac-address = [02 a1 a2 a3 a4 a5];
+ clocks = <0x5 0x6>;
+ clock-names = "dma_clk", "ptp_clk";
+ phy-handle = <0x9>;
+ phy-mode = "xgmii";
+ #stream-id-cells = <0x18>;
+ dma-coherent;
+ linux,phandle = <0xb>;
+ phandle = <0xb>;
+ };
+
+ xgmac@e0900000 {
+ status = "disabled";
+ compatible = "amd,xgbe-seattle-v1a";
+ reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
+ interrupts = <0x0 0x144 0x4>,
+ <0x0 0x155 0x1>,
+ <0x0 0x156 0x1>,
+ <0x0 0x157 0x1>,
+ <0x0 0x158 0x1>;
+ amd,per-channel-interrupt;
+ mac-address = [02 b1 b2 b3 b4 b5];
+ clocks = <0x7 0x8>;
+ clock-names = "dma_clk", "ptp_clk";
+ phy-handle = <0xa>;
+ phy-mode = "xgmii";
+ #stream-id-cells = <0x18>;
+ dma-coherent;
+ linux,phandle = <0xc>;
+ phandle = <0xc>;
+ };
+ };
+
+ chosen {
+ stdout-path = "/smb/serial@e1010000";
+ /* Note:
+ * Linux support for pci-probe-only DT is not
+ * stable. Disable this for now and let Linux
+ * take care of the resource assignment.
+ */
+ // linux,pci-probe-only;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ };
+};
Use tabs consistently throughout the Overdrive DTS file, and use CR-LF line endings just like every other file in EDK2. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 866 ++++++++++---------- 1 file changed, 432 insertions(+), 434 deletions(-)