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[209.132.180.67]) by mx.google.com with ESMTP id o64si1864890pga.16.2017.04.06.06.16.56; Thu, 06 Apr 2017 06:16:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934720AbdDFNQi (ORCPT + 6 others); Thu, 6 Apr 2017 09:16:38 -0400 Received: from mail-pg0-f53.google.com ([74.125.83.53]:34044 "EHLO mail-pg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757095AbdDFNQb (ORCPT ); Thu, 6 Apr 2017 09:16:31 -0400 Received: by mail-pg0-f53.google.com with SMTP id 21so36269493pgg.1 for ; Thu, 06 Apr 2017 06:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oNyvOih6c9AGh/s+I5OZj3Lb0Vucmuh8RcDftbFA2Bo=; b=hySPdRWlTIW3uVuJSd//rIplcPUChjNOWvw/K9MbdDdVDvtd1Ujn6jVF5KgDSFY8Ah GiVgocdHP+X8M24NUeGuTd30zokv5JNK+82BP7m8HlwczQO1ys+2iycXx1ufSNpHckMR g6Hqz3gIVWnz3z/kdOSPj7pl9Z3ARGGeFk0Kg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oNyvOih6c9AGh/s+I5OZj3Lb0Vucmuh8RcDftbFA2Bo=; b=oCTCs2Iv/6w1zLIwRVUwFuyqxiZd3wK/n9XIRE+oQZX/U+i3gV6+8GVrOuK0ihlzF2 IWAoKtL3MB3yVKZg+I5wKrdKemSEynHfmWl3ijAXVjBeOYX/5pqQhIHP/HEURFzsjO99 +06oTKTu+aT+wgS20SYe70+7fipUyQKPs/p9UxkuejwgHkIFXg6RE4xRV758PUp+cxz0 Go2Vmqe061OSiMSUr1CVh39e19LoHrx/GtY7+iiprXGDbFWRyz1T708Nm3nRtpDQbdWH HOlSXcNioW2p/+ZHaBf4x0m0gFIFDl8O07Jtj2tC8IVFz0p7st1DTQfuiYoJD7Zqgbrv /vwQ== X-Gm-Message-State: AFeK/H28vBcc66n2x5sWT/05R7gl+sCIupFFdqxzXxLMjaVksB6hWuBfE74uWBwPJfyI3Ie2 X-Received: by 10.99.231.17 with SMTP id b17mr35926852pgi.55.1491484590115; Thu, 06 Apr 2017 06:16:30 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id y6sm4018940pgc.40.2017.04.06.06.16.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:16:29 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paul Burton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.9 3/7] MIPS: Only change $28 to thread_info if coming from user mode Date: Thu, 6 Apr 2017 18:46:09 +0530 Message-Id: <1491484573-6228-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> References: <1491484573-6228-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matt Redfearn The SAVE_SOME macro is used to save the execution context on all exceptions. If an exception occurs while executing user code, the stack is switched to the kernel's stack for the current task, and register $28 is switched to point to the current_thread_info, which is at the bottom of the stack region. If the exception occurs while executing kernel code, the stack is left, and this change ensures that register $28 is not updated. This is the correct behaviour when the kernel can be executing on the separate irq stack, because the thread_info will not be at the base of it. With this change, register $28 is only switched to it's kernel conventional usage of the currrent thread info pointer at the point at which execution enters kernel space. Doing it on every exception was redundant, but OK without an IRQ stack, but will be erroneous once that is introduced. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14742/ Signed-off-by: Ralf Baechle (cherry picked from commit 510d86362a27577f5ee23f46cfb354ad49731e61) Signed-off-by: Amit Pundir --- arch/mips/include/asm/stackframe.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index eebf395..2f182bd 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -216,12 +216,19 @@ LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) + + /* Set thread_info if we're coming from user mode */ + mfc0 k0, CP0_STATUS + sll k0, 3 /* extract cu0 bit */ + bltz k0, 9f + ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ #endif +9: .set pop .endm