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[209.132.180.67]) by mx.google.com with ESMTP id a96si1939554pli.151.2017.04.06.06.53.08; Thu, 06 Apr 2017 06:53:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934831AbdDFNxG (ORCPT + 6 others); Thu, 6 Apr 2017 09:53:06 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:35382 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753945AbdDFNwg (ORCPT ); Thu, 6 Apr 2017 09:52:36 -0400 Received: by mail-pg0-f52.google.com with SMTP id 81so37120774pgh.2 for ; Thu, 06 Apr 2017 06:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bqJHojYH4zH27VAYD/IIz6NoUGefaNIbta7z6UHc7+U=; b=Z2dLnJ6+CfMzzWIqTVfV04BF/8ZaXDmzXlfANvLdUSAAmAO2MhfWO4bjjqtRR5p51j fAiwt/w4rmDQVwYNcRkhrFEGiP4emRuIywitSgy49eKu/ob79nQPFRe+4OCKK2Yf14YY eQzSb0ZZ1QFc/FYf+VJp7lncBjrv1ql4M5uZ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bqJHojYH4zH27VAYD/IIz6NoUGefaNIbta7z6UHc7+U=; b=ZSdGKxMj5LOGChUr1hFiFuLf/H3pW3ZW2jxjau/hmuOwcO/j98JaEneuQJ9rDDu9tz XGzKO2JdHHBXNJtK/DMCLuLic4PeFD6SmtZ52QT/BX/dj3SAEHia3dZT/yVuuwgj1q0s Sl/FGFDVbb/24kbRq7jT1tAlIY62MOiyfnzwAvLaMABAJ+1UdAqJSv2jYh7iBbc4EdCX ZHHYpnTw/qHd/Sm/KB5f/ahBJ+fgO1HCX2fyOLLqMz7A97bUCBgBsqWT92PMfChyaKUP lzmJsXDr+i1qOJAM2uxdRy/PccnDvLPpelatELsrGXw+bxNnyUJfuOq/BJhi7oiyZ6ws lq/w== X-Gm-Message-State: AFeK/H2sHseUpISqH6NjZnCalTq2GQi9jj+t8Wyx7m8aMWchB4jySY8EHJEFocSiKr6IYIiQ X-Received: by 10.98.49.129 with SMTP id x123mr14249822pfx.45.1491486755449; Thu, 06 Apr 2017 06:52:35 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id v11sm4187210pfi.50.2017.04.06.06.52.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 06:52:34 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paul Burton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.10 4/6] MIPS: Switch to the irq_stack in interrupts Date: Thu, 6 Apr 2017 19:22:12 +0530 Message-Id: <1491486734-15668-5-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491486734-15668-1-git-send-email-amit.pundir@linaro.org> References: <1491486734-15668-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matt Redfearn When enterring interrupt context via handle_int or except_vec_vi, switch to the irq_stack of the current CPU if it is not already in use. The current stack pointer is masked with the thread size and compared to the base or the irq stack. If it does not match then the stack pointer is set to the top of that stack, otherwise this is a nested irq being handled on the irq stack so the stack pointer should be left as it was. The in-use stack pointer is placed in the callee saved register s1. It will be saved to the stack when plat_irq_dispatch is invoked and can be restored once control returns here. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14743/ Signed-off-by: Ralf Baechle (cherry picked from commit dda45f701c9d7ad4ac0bb446e3a96f6df9a468d9) Signed-off-by: Amit Pundir --- arch/mips/kernel/genex.S | 81 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index dc0b296..0a7ba4b 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -187,9 +187,44 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - PTR_LA ra, ret_from_irq - PTR_LA v0, plat_irq_dispatch - jr v0 + + /* + * SAVE_ALL ensures we are using a valid kernel stack for the thread. + * Check if we are already using the IRQ stack. + */ + move s1, sp # Preserve the sp + + /* Get IRQ stack for this CPU */ + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(irq_stack) +#else + lui k1, %highest(irq_stack) + daddiu k1, %higher(irq_stack) + dsll k1, 16 + daddiu k1, %hi(irq_stack) + dsll k1, 16 +#endif + LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_ADDU k1, k0 + LONG_L t0, %lo(irq_stack)(k1) + + # Check if already on IRQ stack + PTR_LI t1, ~(_THREAD_SIZE-1) + and t1, t1, sp + beq t0, t1, 2f + + /* Switch to IRQ stack */ + li t1, _IRQ_STACK_SIZE + PTR_ADD sp, t0, t1 + +2: + jal plat_irq_dispatch + + /* Restore sp */ + move sp, s1 + + j ret_from_irq #ifdef CONFIG_CPU_MICROMIPS nop #endif @@ -262,8 +297,44 @@ NESTED(except_vec_vi_handler, 0, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - PTR_LA ra, ret_from_irq - jr v0 + + /* + * SAVE_ALL ensures we are using a valid kernel stack for the thread. + * Check if we are already using the IRQ stack. + */ + move s1, sp # Preserve the sp + + /* Get IRQ stack for this CPU */ + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(irq_stack) +#else + lui k1, %highest(irq_stack) + daddiu k1, %higher(irq_stack) + dsll k1, 16 + daddiu k1, %hi(irq_stack) + dsll k1, 16 +#endif + LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_ADDU k1, k0 + LONG_L t0, %lo(irq_stack)(k1) + + # Check if already on IRQ stack + PTR_LI t1, ~(_THREAD_SIZE-1) + and t1, t1, sp + beq t0, t1, 2f + + /* Switch to IRQ stack */ + li t1, _IRQ_STACK_SIZE + PTR_ADD sp, t0, t1 + +2: + jal plat_irq_dispatch + + /* Restore sp */ + move sp, s1 + + j ret_from_irq END(except_vec_vi_handler) /*