From patchwork Sat Apr 8 19:13:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 97054 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp775104qgd; Sat, 8 Apr 2017 12:13:51 -0700 (PDT) X-Received: by 10.84.224.136 with SMTP id s8mr1922285plj.93.1491678831390; Sat, 08 Apr 2017 12:13:51 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 188si8799432pgj.71.2017.04.08.12.13.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Apr 2017 12:13:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gdb-patches-return-138109-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-138109-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-138109-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; q=dns; s=default; b=xrJWa+K1xWhCUJxOg6JG+UppzwSdc n3QmLBZajnFM7EOlzvU155FEej6pE926OLr5jLJHSJ0xPVFbpQoLJqT/nVE/nHqQ NrU8hrfIObEWbUYFRCdWfyTiLJWYvD3XP/tQYlMlKa/OkLBRmzk1JmT3bNMt5KNp X7FumuvadyRdac= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; s=default; bh=+/fmUJT7SqcD7YqAQtKvdeRP1aA=; b=Pog n3vdNhxE+QSLshiv0vtxY5HVixxQ7U6xS62/TyoQTn+VUnEhPrpZokfg8qx+JyF6 XH+KeuQFpZP5Lb9IeLeg/vM9/33i9nlBUYAmUbtpg1JAEvFJ7NaorxiPbMdvk1/n VnpL7yYEDQCe8BFnk7kc0mcfnWtcaD10LXBsRD+s= Received: (qmail 130033 invoked by alias); 8 Apr 2017 19:13:39 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 130018 invoked by uid 89); 8 Apr 2017 19:13:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-lf0-f50.google.com Received: from mail-lf0-f50.google.com (HELO mail-lf0-f50.google.com) (209.85.215.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 08 Apr 2017 19:13:36 +0000 Received: by mail-lf0-f50.google.com with SMTP id q141so25193753lfe.2 for ; Sat, 08 Apr 2017 12:13:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=19hfEO1VAjxndvtSBWrk4m9xPD3Yeufi8pxIYWRMxfM=; b=Epxa4Cb0kP0fllSy5UJQ98Du3PWMdsDZJCUKLP8oDjhNCOPwMSjPAw4AVgC0WEqiTl fVsqlghHvBwqcOSOAkZD3fvFcVIICPHDUz1lKoz5GWi7xW4Ka3VEKa5Pl4dlAKvxvUZX 3dZo+x8E2NFcWEQH+Ad50KJJ0wwZVkCP3RYj4g4U/WrPVSYtUaNXMbZb4TST7HWI8p9c MK/oTsvcmbpZJOVpNb+m+XpFVphUZZQCsRzdCp146HMtOsNL0TK5Kmf2rQVxKv2Z+0S2 LcVa3scm+IQLfhdjGQ41c+QCOuo5+06/xlDBa8DXCFaKZKEPb85mO6udmmPF+W2dWcmy QnGA== X-Gm-Message-State: AFeK/H3j32++fSzZnM78GdZZMdQC6rXk2GtbWCMm7CH0Q1YPpmhyepyf4O5H3mSsfx+PftVYi5GFSFJSZ7/5V1/b X-Received: by 10.25.215.89 with SMTP id o86mr16809368lfg.92.1491678815496; Sat, 08 Apr 2017 12:13:35 -0700 (PDT) MIME-Version: 1.0 Received: by 10.25.162.145 with HTTP; Sat, 8 Apr 2017 12:13:34 -0700 (PDT) From: Jim Wilson Date: Sat, 8 Apr 2017 12:13:34 -0700 Message-ID: Subject: [PATCH] aarch64 sim add support for fcvtl To: gdb-patches@sourceware.org This adds missing support for the fcvtl and fcvtl2 instructions. The new testcase fails without the patch and works with the patch. The GCC C testsuite unexpected failures drop from 1431 to 1427 (-4). Jim 2017-04-08 Jim Wilson sim/aarch64/ * simulator.c (do_vec_FCVTL): New. (do_vec_op1): Call do_vec_FCVTL. sim/testsuite/sim/aarch64/ * fcvtl.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index c2e02b1..16d8d8d 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -5468,6 +5468,47 @@ do_vec_ADDP (sim_cpu *cpu) } } +/* Float point vector convert to longer (precision). */ +static void +do_vec_FCVTL (sim_cpu *cpu) +{ + /* instr[31] = 0 + instr[30] = half (0) / all (1) + instr[29,23] = 00 1110 0 + instr[22] = single (0) / double (1) + instr[21,10] = 10 0001 0111 10 + instr[9,5] = Rn + instr[4,0] = Rd. */ + + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + unsigned full = INSTR (30, 30); + unsigned i; + + NYI_assert (31, 31, 0); + NYI_assert (29, 23, 0x1C); + NYI_assert (21, 10, 0x85E); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (INSTR (22, 22)) + { + for (i = 0; i < 2; i++) + aarch64_set_vec_double (cpu, rd, i, + aarch64_get_vec_float (cpu, rn, i + 2*full)); + } + else + { + HALT_NYI; + +#if 0 + /* TODO: Implement missing half-float support. */ + for (i = 0; i < 4; i++) + aarch64_set_vec_float (cpu, rd, i, + aarch64_get_vec_halffloat (cpu, rn, i + 4*full)); +#endif + } +} + static void do_vec_FABS (sim_cpu *cpu) { @@ -5717,6 +5758,13 @@ do_vec_op1 (sim_cpu *cpu) case 0x33: do_vec_FMLA (cpu); return; case 0x35: do_vec_fadd (cpu); return; + case 0x1E: + switch (INSTR (20, 16)) + { + case 0x01: do_vec_FCVTL (cpu); return; + default: HALT_NYI; + } + case 0x2E: switch (INSTR (20, 16)) { diff --git a/sim/testsuite/sim/aarch64/fcvtl.s b/sim/testsuite/sim/aarch64/fcvtl.s new file mode 100644 index 0000000..8febc08 --- /dev/null +++ b/sim/testsuite/sim/aarch64/fcvtl.s @@ -0,0 +1,59 @@ +# mach: aarch64 + +# Check the FP convert to longer precision: fcvtl, fcvtl2. +# Test values 1.5, -1.5, INTMAX, and INT_MIN. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 1069547520 + .word 3217031168 + .word 1325400064 + .word 3472883712 +d1p5: + .word 0 + .word 1073217536 +dm1p5: + .word 0 + .word -1074266112 +dimax: + .word 0 + .word 1105199104 +dimin: + .word 0 + .word -1042284544 + + start + adrp x0, input + add x0, x0, #:lo12:input + ld1 {v0.4s}, [x0] + + fcvtl v1.2d, v0.2s + mov x1, v1.d[0] + adrp x2, d1p5 + ldr x3, [x2, #:lo12:d1p5] + cmp x1, x3 + bne .Lfailure + mov x1, v1.d[1] + adrp x2, dm1p5 + ldr x3, [x2, #:lo12:dm1p5] + cmp x1, x3 + bne .Lfailure + + fcvtl2 v2.2d, v0.4s + mov x1, v2.d[0] + adrp x2, dimax + ldr x3, [x2, #:lo12:dimax] + cmp x1, x3 + bne .Lfailure + mov x1, v2.d[1] + adrp x2, dimin + ldr x3, [x2, #:lo12:dimin] + cmp x1, x3 + bne .Lfailure + + pass +.Lfailure: + fail