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[05/32] phy: sun4i-usb: change PHYCTL register clearing code

Message ID 20170410131823.26485-6-kishon@ti.com
State Accepted
Commit d699c1d0860aa8b3031d56ec861e6c2f2e37df95
Headers show
Series [01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header | expand

Commit Message

Kishon Vijay Abraham I April 10, 2017, 1:17 p.m. UTC 
From: Icenowy Zheng <icenowy@aosc.xyz>


It seems that all SoCs with the PHYCTL register offset as 0x10 need the
PHYCTL register to be cleared before it's written.

Change PHYCTL register clearing code to judge whether clearing is needed
based on the PHYCTL offset.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

---
 drivers/phy/phy-sun4i-usb.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

-- 
2.11.0
diff mbox series

Patch

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index a21b5f24a340..62b4d25448c6 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -188,10 +188,8 @@  static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
 
 	spin_lock_irqsave(&phy_data->reg_lock, flags);
 
-	if (phy_data->cfg->type == sun8i_a33_phy ||
-	    phy_data->cfg->type == sun50i_a64_phy ||
-	    phy_data->cfg->type == sun8i_v3s_phy) {
-		/* A33 or A64 needs us to set phyctl to 0 explicitly */
+	if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
+		/* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 		writel(0, phyctl);
 	}