From patchwork Fri Apr 21 09:18:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liviu Dudau X-Patchwork-Id: 97882 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp226090qgf; Fri, 21 Apr 2017 02:19:36 -0700 (PDT) X-Received: by 10.99.3.8 with SMTP id 8mr11406468pgd.208.1492766376313; Fri, 21 Apr 2017 02:19:36 -0700 (PDT) Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id v190si9750427pfb.267.2017.04.21.02.19.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Apr 2017 02:19:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83ECB6E409; Fri, 21 Apr 2017 09:19:10 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by gabe.freedesktop.org (Postfix) with ESMTPS id 36EBE6E3ED for ; Fri, 21 Apr 2017 09:18:52 +0000 (UTC) Received: from e110455-lin.cambridge.arm.com (e110455-lin.cambridge.arm.com [10.2.131.9]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v3L9ImWa025801; Fri, 21 Apr 2017 10:18:49 +0100 From: Liviu Dudau To: Brian Starkey Subject: [PATCH 11/12] drm: mali-dp: Enable image enhancement when scaling Date: Fri, 21 Apr 2017 10:18:47 +0100 Message-Id: <20170421091848.4666-12-Liviu.Dudau@arm.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170421091848.4666-1-Liviu.Dudau@arm.com> References: <20170421091848.4666-1-Liviu.Dudau@arm.com> Cc: Mihail Atanassov , Mali DP Maintainers , DRI devel X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mihail Atanassov Apply image enhacement when we are upscaling by a factor of 2 or more in either direction. Signed-off-by: Mihail Atanassov Signed-off-by: Liviu Dudau --- drivers/gpu/drm/arm/malidp_crtc.c | 7 ++++++- drivers/gpu/drm/arm/malidp_drv.c | 3 +++ drivers/gpu/drm/arm/malidp_hw.h | 20 ++++++++++++++++++++ drivers/gpu/drm/arm/malidp_regs.h | 13 +++++++++++++ 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c index ceee2a77bfb4..b0f0365efd23 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -288,6 +288,9 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, if (!(h_upscale_factor >> 16) || !(v_upscale_factor >> 16)) return -EINVAL; + s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 || + (v_upscale_factor >> 16) >= 2); + s->input_w = pstate->src_w >> 16; s->input_h = pstate->src_h >> 16; s->output_w = pstate->crtc_w; @@ -530,9 +533,11 @@ int malidp_crtc_init(struct drm_device *drm) drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE); - /* No inverse-gamma: it is per-plane */ + /* No inverse-gamma: it is per-plane. */ drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE); + malidp_se_set_enh_coeffs(malidp->dev); + return 0; crtc_cleanup_planes: diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index baca2dce1b92..0d3eb537d08b 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -138,6 +138,9 @@ static void malidp_atomic_commit_se_config(struct drm_crtc *crtc, val = malidp_hw_read(hwdev, se_control); val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN; + val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK); + val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0; + val |= MALIDP_SE_RGBO_IF_EN; malidp_hw_write(hwdev, val, se_control); diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h index 52a65a8a056f..a93ae0a951a3 100644 --- a/drivers/gpu/drm/arm/malidp_hw.h +++ b/drivers/gpu/drm/arm/malidp_hw.h @@ -71,6 +71,7 @@ enum malidp_scaling_coeff_set { struct malidp_se_config { u8 scale_enable : 1; + u8 enhancer_enable : 1; u8 hcoeff : 3; u8 vcoeff : 3; u8 plane_src_id; @@ -295,6 +296,25 @@ malidp_se_select_coeffs(u32 upscale_factor) #undef FP_0_50000 #undef FP_0_66667 #undef FP_1_00000 + +static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) +{ + static const s32 enhancer_coeffs[] = { + -8, -8, -8, -8, 128, -8, -8, -8, -8 + }; + u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) | + MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL); + u32 image_enh = hwdev->map.se_base + + ((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? + 0x10 : 0xC) + MALIDP_SE_IMAGE_ENH; + u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0; + int i; + + malidp_hw_write(hwdev, val, image_enh); + for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i) + malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); +} + /* * background color components are defined as 12bits values, * they will be shifted right when stored on hardware that diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 91d2ba5729bf..2039f857f77d 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -109,6 +109,8 @@ /* Scaling engine registers and masks. */ #define MALIDP_SE_SCALING_EN (1 << 0) #define MALIDP_SE_ALPHA_EN (1 << 1) +#define MALIDP_SE_ENH_MASK 3 +#define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2) #define MALIDP_SE_RGBO_IF_EN (1 << 4) #define MALIDP550_SE_CTL_SEL_MASK 7 #define MALIDP550_SE_CTL_VCSEL(x) \ @@ -139,6 +141,17 @@ #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) +/* Enhance coeffents reigster offset */ +#define MALIDP_SE_IMAGE_ENH 0x3C +/* ENH_LIMITS offset 0x0 */ +#define MALIDP_SE_ENH_LOW_LEVEL 24 +#define MALIDP_SE_ENH_HIGH_LEVEL 63 +#define MALIDP_SE_ENH_LIMIT_MASK 0xfff +#define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \ + ((x) & MALIDP_SE_ENH_LIMIT_MASK) +#define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \ + (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) +#define MALIDP_SE_ENH_COEFF0 0x04 /* register offsets and bits specific to DP500 */ #define MALIDP500_ADDR_SPACE_SIZE 0x01000