diff mbox series

[RFC,1/3] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access()

Message ID 1493051615-30715-2-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show
Series split core mmu_idx from ARMMMUIdx values | expand

Commit Message

Peter Maydell April 24, 2017, 4:33 p.m. UTC
When identifying the DFSR format for an alignment fault, use
the mmu index that we are passed, rather than calling cpu_mmu_index()
to get the mmu index for the current CPU state. This doesn't actually
make any difference since the only cases where the current MMU index
differs from the index used for the load are the "unprivileged
load/store" instructions, and in that case the mmu index may
differ but the translation regime is the same (apart from the
"use from Hyp mode" case which is UNPREDICTABLE).
However it's the more logical thing to do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.7.4

Comments

Richard Henderson April 26, 2017, 9:57 a.m. UTC | #1
On 04/24/2017 06:33 PM, Peter Maydell wrote:
> When identifying the DFSR format for an alignment fault, use

> the mmu index that we are passed, rather than calling cpu_mmu_index()

> to get the mmu index for the current CPU state. This doesn't actually

> make any difference since the only cases where the current MMU index

> differs from the index used for the load are the "unprivileged

> load/store" instructions, and in that case the mmu index may

> differ but the translation regime is the same (apart from the

> "use from Hyp mode" case which is UNPREDICTABLE).

> However it's the more logical thing to do.

> 

> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>

> ---

>   target/arm/op_helper.c | 2 +-

>   1 file changed, 1 insertion(+), 1 deletion(-)


Reviewed-by: Richard Henderson <rth@twiddle.net>



r~
diff mbox series

Patch

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 156b825..de24815 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -208,7 +208,7 @@  void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
     /* the DFSR for an alignment fault depends on whether we're using
      * the LPAE long descriptor format, or the short descriptor format
      */
-    if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
+    if (arm_s1_regime_using_lpae_format(env, mmu_idx)) {
         env->exception.fsr = (1 << 9) | 0x21;
     } else {
         env->exception.fsr = 0x1;