| Message ID | 1493122030-32191-2-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | armv7m: Implement MPU support | expand |
On Tue, Apr 25, 2017 at 5:06 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > When identifying the DFSR format for an alignment fault, use > the mmu index that we are passed, rather than calling cpu_mmu_index() > to get the mmu index for the current CPU state. This doesn't actually > make any difference since the only cases where the current MMU index > differs from the index used for the load are the "unprivileged > load/store" instructions, and in that case the mmu index may > differ but the translation regime is the same (apart from the > "use from Hyp mode" case which is UNPREDICTABLE). > However it's the more logical thing to do. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Thanks, Alistair > --- > target/arm/op_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index 156b825..de24815 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -208,7 +208,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > /* the DFSR for an alignment fault depends on whether we're using > * the LPAE long descriptor format, or the short descriptor format > */ > - if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { > + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { > env->exception.fsr = (1 << 9) | 0x21; > } else { > env->exception.fsr = 0x1; > -- > 2.7.4 > >
On 05/02/2017 07:05 PM, Alistair Francis wrote: > On Tue, Apr 25, 2017 at 5:06 AM, Peter Maydell <peter.maydell@linaro.org> wrote: >> When identifying the DFSR format for an alignment fault, use >> the mmu index that we are passed, rather than calling cpu_mmu_index() >> to get the mmu index for the current CPU state. This doesn't actually >> make any difference since the only cases where the current MMU index >> differs from the index used for the load are the "unprivileged >> load/store" instructions, and in that case the mmu index may >> differ but the translation regime is the same (apart from the >> "use from Hyp mode" case which is UNPREDICTABLE). >> However it's the more logical thing to do. >> >> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Thanks, > > Alistair > >> --- >> target/arm/op_helper.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c >> index 156b825..de24815 100644 >> --- a/target/arm/op_helper.c >> +++ b/target/arm/op_helper.c >> @@ -208,7 +208,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, >> /* the DFSR for an alignment fault depends on whether we're using >> * the LPAE long descriptor format, or the short descriptor format >> */ >> - if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { >> + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { >> env->exception.fsr = (1 << 9) | 0x21; >> } else { >> env->exception.fsr = 0x1; >> -- >> 2.7.4 >> >> >
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 156b825..de24815 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -208,7 +208,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ - if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { + if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { env->exception.fsr = (1 << 9) | 0x21; } else { env->exception.fsr = 0x1;
When identifying the DFSR format for an alignment fault, use the mmu index that we are passed, rather than calling cpu_mmu_index() to get the mmu index for the current CPU state. This doesn't actually make any difference since the only cases where the current MMU index differs from the index used for the load are the "unprivileged load/store" instructions, and in that case the mmu index may differ but the translation regime is the same (apart from the "use from Hyp mode" case which is UNPREDICTABLE). However it's the more logical thing to do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4