From patchwork Fri May 5 19:47:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 98718 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp293323qge; Fri, 5 May 2017 12:49:55 -0700 (PDT) X-Received: by 10.98.97.195 with SMTP id v186mr18953783pfb.81.1494013795808; Fri, 05 May 2017 12:49:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si2689373pgp.198.2017.05.05.12.49.55; Fri, 05 May 2017 12:49:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755767AbdEETs5 (ORCPT + 6 others); Fri, 5 May 2017 15:48:57 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:50742 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753654AbdEETsm (ORCPT ); Fri, 5 May 2017 15:48:42 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.129]) with ESMTPA (Nemesis) id 0Lsc93-1e4EhO2VIX-012H12; Fri, 05 May 2017 21:48:35 +0200 From: Arnd Bergmann To: Ben Hutchings Cc: stable@vger.kernel.org, Arnd Bergmann , Russell King Subject: [PATCH 3.16-stable 78/87] ARM: 8296/1: cache-l2x0: clean up aurora cache handling Date: Fri, 5 May 2017 21:47:36 +0200 Message-Id: <20170505194745.3627137-79-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170505194745.3627137-1-arnd@arndb.de> References: <20170505194745.3627137-1-arnd@arndb.de> X-Provags-ID: V03:K0:8+Q926C+9XIKYfeMXtk4GszX0xGf+/oMalbWrjUKX2OcPJVkzOo vhIXzbBe0w1jp4Ffc4Dfu7587ToQQ9/sOw/hmP/mpOnVQo/lwORx3UdBiTAmLsyfTKh2qlW qJtfZ9F9mtOZGOv9V0hTzDJQB8l7nlsa61Y9aA4p1X3tr0ii0bpFDoUn3hsW8m3oOPYG7TD IMjn84Sw9D3AgkRnNtSXg== X-UI-Out-Filterresults: notjunk:1; V01:K0:oNeHURWFMjI=:J41B1Ku5PvMUDQmJJPzBp0 jbrEb8+ToFKJcBBan7Sh+1FYa7mVwuYI5jgNIZWTw9X2bjwMAtC8bPeKRlvmUGUDRmaZVPeNF QuTl3QUEnJLM11kk2ekyp368Mz6XcteFwR5AVX3Z5i/6YXu+ZPpXY+1wVbdsOVHMN8Oqw97R8 GsdCPt724PULnVlpptssOlMwI6mFBIip1fWk6W/4bft4ElC1P45IT4H2sXT3ZfWTgiddEApb8 scIf/bquTCVaaj0rozASu1IVFk7Lr1e6jleLj/k8ytooEQpPvj4bLUW/aqUqqDg4J/Pbto8Y0 NcPHSCWqkgmNVMvPp2+BCHANqQk69ora3oR1AOCNMdaNrImPFx5+ALlDx+MlF0q08Y9JAFIgP TX6FglP3Bre4pHSzG0VrjI4VZnUCgdRM7ACcETFQyG4i+wmAiDpP9mkV2WGZmh79leq7LcNHi luCLZnplXCLlTLUsqk0GRwyr7wrkVBR3A7E6sm+jYSKD4UJVw/0yukeaVKe9k/s4OnOG9jZmp esoQPGVjys57/4y27N2icQIUoMRY/+66EB95j7WytPfS3m5lK/0Koq+PQraeb78AbUnATplmk I7/s81mT71fQ1/73yegIEczNe+y3lFCTHwBk86hDpJ5keF8GE0VTqPMo/ZI40sY3kwlmB7BJI ow3aQyHuFenxW6M48VFIqEVbJXThzd14LIt+AFEI4G1+9NJ9O7g2774/KkaLDtEGbbuU= Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Commit 20e783e39e55c2615fb61d1b3d139ee9edcf6772 upstream. The aurora cache controller is the only remaining user of a couple of functions in this file and are completely unused when that is disabled, leading to build warnings: arch/arm/mm/cache-l2x0.c:167:13: warning: 'l2x0_cache_sync' defined but not used [-Wunused-function] arch/arm/mm/cache-l2x0.c:184:13: warning: 'l2x0_flush_all' defined but not used [-Wunused-function] arch/arm/mm/cache-l2x0.c:194:13: warning: 'l2x0_disable' defined but not used [-Wunused-function] With the knowledge that the code is now aurora-specific, we can simplify it noticeably: - The pl310 errata workarounds are not needed on aurora and can be removed - As confirmed by Thomas Petazzoni from the data sheet, the cache_wait() macro is never needed. - No need to hold the lock across atomic cache sync - We can load the l2x0_base into a local variable across operations There should be no functional change in this patch, but readability and the generated object code improves, along with avoiding the warnings. (on Armada 370 RD and Armada XP GP, boot tested, plus a little bit of DMA traffic by reading data from a SD card) Acked-by: Thomas Petazzoni Tested-by: Thomas Petazzoni Signed-off-by: Arnd Bergmann Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 111 ++++++++++++++++------------------------------- 1 file changed, 38 insertions(+), 73 deletions(-) -- 2.9.0 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 7c3fb41a462e..011490e7204d 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -135,73 +135,6 @@ static void l2c_disable(void) dsb(st); } -#ifdef CONFIG_CACHE_PL310 -static inline void cache_wait(void __iomem *reg, unsigned long mask) -{ - /* cache operations by line are atomic on PL310 */ -} -#else -#define cache_wait l2c_wait_mask -#endif - -static inline void cache_sync(void) -{ - void __iomem *base = l2x0_base; - - writel_relaxed(0, base + sync_reg_offset); - cache_wait(base + L2X0_CACHE_SYNC, 1); -} - -#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) -static inline void debug_writel(unsigned long val) -{ - l2c_set_debug(l2x0_base, val); -} -#else -/* Optimised out for non-errata case */ -static inline void debug_writel(unsigned long val) -{ -} -#endif - -static void l2x0_cache_sync(void) -{ - unsigned long flags; - - raw_spin_lock_irqsave(&l2x0_lock, flags); - cache_sync(); - raw_spin_unlock_irqrestore(&l2x0_lock, flags); -} - -static void __l2x0_flush_all(void) -{ - debug_writel(0x03); - __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); - cache_sync(); - debug_writel(0x00); -} - -static void l2x0_flush_all(void) -{ - unsigned long flags; - - /* clean all ways */ - raw_spin_lock_irqsave(&l2x0_lock, flags); - __l2x0_flush_all(); - raw_spin_unlock_irqrestore(&l2x0_lock, flags); -} - -static void l2x0_disable(void) -{ - unsigned long flags; - - raw_spin_lock_irqsave(&l2x0_lock, flags); - __l2x0_flush_all(); - l2c_write_sec(0, l2x0_base, L2X0_CTRL); - dsb(st); - raw_spin_unlock_irqrestore(&l2x0_lock, flags); -} - static void l2c_save(void __iomem *base) { l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); @@ -1126,14 +1059,15 @@ static unsigned long calc_range_end(unsigned long start, unsigned long end) static void aurora_pa_range(unsigned long start, unsigned long end, unsigned long offset) { + void __iomem *base = l2x0_base; unsigned long flags; raw_spin_lock_irqsave(&l2x0_lock, flags); - writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); - writel_relaxed(end, l2x0_base + offset); + writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG); + writel_relaxed(end, base + offset); raw_spin_unlock_irqrestore(&l2x0_lock, flags); - cache_sync(); + writel_relaxed(0, base + AURORA_SYNC_REG); } static void aurora_inv_range(unsigned long start, unsigned long end) @@ -1193,6 +1127,37 @@ static void aurora_flush_range(unsigned long start, unsigned long end) } } +static void aurora_flush_all(void) +{ + void __iomem *base = l2x0_base; + unsigned long flags; + + /* clean all ways */ + raw_spin_lock_irqsave(&l2x0_lock, flags); + __l2c_op_way(base + L2X0_CLEAN_INV_WAY); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); + + writel_relaxed(0, base + AURORA_SYNC_REG); +} + +static void aurora_cache_sync(void) +{ + writel_relaxed(0, l2x0_base + AURORA_SYNC_REG); +} + +static void aurora_disable(void) +{ + void __iomem *base = l2x0_base; + unsigned long flags; + + raw_spin_lock_irqsave(&l2x0_lock, flags); + __l2c_op_way(base + L2X0_CLEAN_INV_WAY); + writel_relaxed(0, base + AURORA_SYNC_REG); + l2c_write_sec(0, base, L2X0_CTRL); + dsb(st); + raw_spin_unlock_irqrestore(&l2x0_lock, flags); +} + static void aurora_save(void __iomem *base) { l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); @@ -1267,9 +1232,9 @@ static const struct l2c_init_data of_aurora_with_outer_data __initconst = { .inv_range = aurora_inv_range, .clean_range = aurora_clean_range, .flush_range = aurora_flush_range, - .flush_all = l2x0_flush_all, - .disable = l2x0_disable, - .sync = l2x0_cache_sync, + .flush_all = aurora_flush_all, + .disable = aurora_disable, + .sync = aurora_cache_sync, .resume = aurora_resume, }, };