From patchwork Fri May 5 19:47:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 98719 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp293328qge; Fri, 5 May 2017 12:49:56 -0700 (PDT) X-Received: by 10.98.30.3 with SMTP id e3mr18579714pfe.48.1494013796795; Fri, 05 May 2017 12:49:56 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si2689373pgp.198.2017.05.05.12.49.56; Fri, 05 May 2017 12:49:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755720AbdEETs4 (ORCPT + 6 others); Fri, 5 May 2017 15:48:56 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:50371 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755767AbdEETsm (ORCPT ); Fri, 5 May 2017 15:48:42 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.129]) with ESMTPA (Nemesis) id 0M1eYM-1dvfya2xnG-00tiRb; Fri, 05 May 2017 21:48:34 +0200 From: Arnd Bergmann To: Ben Hutchings Cc: stable@vger.kernel.org, Ard Biesheuvel , Russell King , Arnd Bergmann Subject: [PATCH 3.16-stable 75/87] ARM: 8221/1: PJ4: allow building in Thumb-2 mode Date: Fri, 5 May 2017 21:47:33 +0200 Message-Id: <20170505194745.3627137-76-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170505194745.3627137-1-arnd@arndb.de> References: <20170505194745.3627137-1-arnd@arndb.de> X-Provags-ID: V03:K0:ASb8VqWIVrWJVTNIv6eve4o5vJg0m5l8A1hLacBnhcIz6L/k5Zs up9VwKnXTNG8hGZzQFoVpcvoQZzf8PkFjeLDNBkl4LQG3TexCe3fqD78qNdxCrbk3L0H2bm cEHhXujk3fMa6Pmf0Fs2vUM1pAhYHk7fofjfM7oohMkxZ3TqoVghr6o/Dh0rrMtpc12E+MW 9Jpce88Ti/t2fUngqS2JA== X-UI-Out-Filterresults: notjunk:1; V01:K0:VifYnS3kBBU=:+k/rrC8gmiotqKAQygWL4K 1b89L6qMM0ltQAbsp0G5IPeZaho1zKyULFxBRv7g+eWKjBw0CXDk7rMKl16Vo4cLmgygsC8TO WNjWD1faZVI38/2ryhHico/jLR6nGqXKoAlkruc0uj/dCB0xIRYTw46LRTcZkPeoZIrdN7xPx MGKmAu2QMRwG1rSjdz6H/um03qv1sKAsgks+hSwXM0RJRZvBJuEvuFHNxgf6tuRpQIIThJuG4 jKoidXxvL/vpBbcgKS4ugvOhBa0CtRZ8lV9X9glD9vNdbOVX1Fcd27BVKRMeSvvE/bpnjMRuz imvVuLMjyZ89D5fVZ4rAuNenjJTHGZea7+4BHr5kR/psdTomDgQIWkoKTlsM0E0rks6ayoIu0 IGE+S1cdKnkYTdU+NGIM+UFIBUBVEvb7jgutRAorXsdTu5JK5FMgjDhL6zZhKbdT+UxTah6jl HBgY4nuyfuLvEQnmAGfP7PPwa4vyGBoLzLT6EahWFduvfYsnuJVaksaW8CsEUkQ6j71P1CfZA UULCo/M2vxYQzg4Y2UTZ5Sh8IgOMcL7D0y/iLcC9gfySYtHdKEvjW22Ol6HypMpbUJKNLy25J tXh1aYrrMS0ECsZvHs+BZ2nSocVNB5VQLsEbnCIXDv+A5Xvum8CT+uCwZLzu+7slzL531ks4g pBvVsHIbHbjOym71mIdtpRTqDlqtClrjs/wV2JAh8Ewe0YwCR+Jcp15cnnsX4/fl1914= Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Ard Biesheuvel Commit 69bbf2ab20389418327484288d8730732e4f3dd0 upstream. Two files that get included when building the multi_v7_defconfig target fail to build when selecting THUMB2_KERNEL for this configuration. In both cases, we can just build the file as ARM code, as none of its symbols are exported to modules, so there are no interworking concerns. In the iwmmxt.S case, add ENDPROC() declarations so the symbols are annotated as functions, resulting in the linker to emit the appropriate mode switches. Acked-by: Nicolas Pitre Tested-by: Olof Johansson Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King Signed-off-by: Arnd Bergmann --- arch/arm/kernel/Makefile | 1 + arch/arm/kernel/iwmmxt.S | 13 +++++++++++++ 2 files changed, 14 insertions(+) -- 2.9.0 diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 03120e656aea..2ecc7d15bc09 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o +CFLAGS_pj4-cp0.o := -marm AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index 2b32978ae905..d65bb940d797 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -58,6 +58,7 @@ #define MMX_SIZE (0x98) .text + .arm /* * Lazy switching of Concan coprocessor context @@ -182,6 +183,8 @@ concan_load: tmcr wCon, r2 mov pc, lr +ENDPROC(iwmmxt_task_enable) + /* * Back up Concan regs to save area and disable access to them * (mainly for gdb or sleep mode usage) @@ -232,6 +235,8 @@ ENTRY(iwmmxt_task_disable) 1: msr cpsr_c, ip @ restore interrupt mode ldmfd sp!, {r4, pc} +ENDPROC(iwmmxt_task_disable) + /* * Copy Concan state to given memory address * @@ -268,6 +273,8 @@ ENTRY(iwmmxt_task_copy) msr cpsr_c, ip @ restore interrupt mode mov pc, r3 +ENDPROC(iwmmxt_task_copy) + /* * Restore Concan state from given memory address * @@ -304,6 +311,8 @@ ENTRY(iwmmxt_task_restore) msr cpsr_c, ip @ restore interrupt mode mov pc, r3 +ENDPROC(iwmmxt_task_restore) + /* * Concan handling on task switch * @@ -335,6 +344,8 @@ ENTRY(iwmmxt_task_switch) mrc p15, 0, r1, c2, c0, 0 sub pc, lr, r1, lsr #32 @ cpwait and return +ENDPROC(iwmmxt_task_switch) + /* * Remove Concan ownership of given task * @@ -353,6 +364,8 @@ ENTRY(iwmmxt_task_release) msr cpsr_c, r2 @ restore interrupts mov pc, lr +ENDPROC(iwmmxt_task_release) + .data concan_owner: .word 0