| Message ID | 20170505194745.3627137-82-arnd@arndb.de |
|---|---|
| State | New |
| Headers | show |
| Series | build warnings and errors | expand |
On Fri, 2017-05-05 at 21:47 +0200, Arnd Bergmann wrote: > From: Ralf Baechle <ralf@linux-mips.org> > > Commit a4d7f14bd8d3316f847c3e0f7020dad95a8a648a upstream. > > When expanding the la or dla pseudo-instruction in a delay slot the GNU > assembler will complain should the pseudo-instruction expand to multiple > actual instructions, since only the first of them will be in the delay > slot leading to the pseudo-instruction being only partially executed if > the branch is taken. Use of PTR_LA in the dec int-handler.S leads to > such warnings: > > arch/mips/dec/int-handler.S: Assembler messages: > arch/mips/dec/int-handler.S:149: Warning: macro instruction expanded into multiple instructions in a branch delay slot > arch/mips/dec/int-handler.S:198: Warning: macro instruction expanded into multiple instructions in a branch delay slot > > Avoid this by open coding the PTR_LA macros. This needed a follow-up fix: commit 68fe55680d0f3342969f49412fceabb90bdfadba Author: Maciej W. Rozycki <macro@linux-mips.org> Date: Sun Jul 30 21:28:15 2017 +0100 MIPS: DEC: Fix an int-handler.S CPU_DADDI_WORKAROUNDS regression which is missing from the 3.12, 3.18 and 4.4 branches. Ben. > Signed-off-by: Ralf Baechle <ralf@linux-mips.org> > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > --- > arch/mips/dec/int-handler.S | 40 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S > index 41a2fa1fa12e..c7953f2aca4f 100644 > --- a/arch/mips/dec/int-handler.S > +++ b/arch/mips/dec/int-handler.S > @@ -146,7 +146,25 @@ > /* > * Find irq with highest priority > */ > - PTR_LA t1,cpu_mask_nr_tbl > + # open coded PTR_LA t1, cpu_mask_nr_tbl > +#if (_MIPS_SZPTR == 32) > + # open coded la t1, cpu_mask_nr_tbl > + lui t1, %hi(cpu_mask_nr_tbl) > + addiu t1, %lo(cpu_mask_nr_tbl) > + > +#endif > +#if (_MIPS_SZPTR == 64) > + # open coded dla t1, cpu_mask_nr_tbl > + .set push > + .set noat > + lui t1, %highest(cpu_mask_nr_tbl) > + lui AT, %hi(cpu_mask_nr_tbl) > + daddiu t1, t1, %higher(cpu_mask_nr_tbl) > + daddiu AT, AT, %lo(cpu_mask_nr_tbl) > + dsll t1, 32 > + daddu t1, t1, AT > + .set pop > +#endif > 1: lw t2,(t1) > nop > and t2,t0 > @@ -195,7 +213,25 @@ > /* > * Find irq with highest priority > */ > - PTR_LA t1,asic_mask_nr_tbl > + # open coded PTR_LA t1,asic_mask_nr_tbl > +#if (_MIPS_SZPTR == 32) > + # open coded la t1, asic_mask_nr_tbl > + lui t1, %hi(asic_mask_nr_tbl) > + addiu t1, %lo(asic_mask_nr_tbl) > + > +#endif > +#if (_MIPS_SZPTR == 64) > + # open coded dla t1, asic_mask_nr_tbl > + .set push > + .set noat > + lui t1, %highest(asic_mask_nr_tbl) > + lui AT, %hi(asic_mask_nr_tbl) > + daddiu t1, t1, %higher(asic_mask_nr_tbl) > + daddiu AT, AT, %lo(asic_mask_nr_tbl) > + dsll t1, 32 > + daddu t1, t1, AT > + .set pop > +#endif > 2: lw t2,(t1) > nop > and t2,t0 -- Ben Hutchings It is a miracle that curiosity survives formal education. - Albert Einstein
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 41a2fa1fa12e..c7953f2aca4f 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -146,7 +146,25 @@ /* * Find irq with highest priority */ - PTR_LA t1,cpu_mask_nr_tbl + # open coded PTR_LA t1, cpu_mask_nr_tbl +#if (_MIPS_SZPTR == 32) + # open coded la t1, cpu_mask_nr_tbl + lui t1, %hi(cpu_mask_nr_tbl) + addiu t1, %lo(cpu_mask_nr_tbl) + +#endif +#if (_MIPS_SZPTR == 64) + # open coded dla t1, cpu_mask_nr_tbl + .set push + .set noat + lui t1, %highest(cpu_mask_nr_tbl) + lui AT, %hi(cpu_mask_nr_tbl) + daddiu t1, t1, %higher(cpu_mask_nr_tbl) + daddiu AT, AT, %lo(cpu_mask_nr_tbl) + dsll t1, 32 + daddu t1, t1, AT + .set pop +#endif 1: lw t2,(t1) nop and t2,t0 @@ -195,7 +213,25 @@ /* * Find irq with highest priority */ - PTR_LA t1,asic_mask_nr_tbl + # open coded PTR_LA t1,asic_mask_nr_tbl +#if (_MIPS_SZPTR == 32) + # open coded la t1, asic_mask_nr_tbl + lui t1, %hi(asic_mask_nr_tbl) + addiu t1, %lo(asic_mask_nr_tbl) + +#endif +#if (_MIPS_SZPTR == 64) + # open coded dla t1, asic_mask_nr_tbl + .set push + .set noat + lui t1, %highest(asic_mask_nr_tbl) + lui AT, %hi(asic_mask_nr_tbl) + daddiu t1, t1, %higher(asic_mask_nr_tbl) + daddiu AT, AT, %lo(asic_mask_nr_tbl) + dsll t1, 32 + daddu t1, t1, AT + .set pop +#endif 2: lw t2,(t1) nop and t2,t0