From patchwork Fri May 5 19:47:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 98724 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp293431qge; Fri, 5 May 2017 12:50:06 -0700 (PDT) X-Received: by 10.98.46.69 with SMTP id u66mr18930261pfu.262.1494013806213; Fri, 05 May 2017 12:50:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494013806; cv=none; d=google.com; s=arc-20160816; b=0/Rsf4Qr0vJOGFV1TEfYAbQX9nuVJl70UZEMcyXgOOfSrZCKGng2zZtuy4mfXtZoPc Bktrcxflzf88hTXFFsE64niNRE0GUNNOLkxLlWIvpRcs1u/IWMRrT79pw6gGoROAvwG6 BNhpIG/OhT+T6kL2IACVys7h38ORgHQP2XxCjKI5+IzD/FfeiYHEq+KiKUfInsNdm/tX NQTcrXk0CVOC/uH2tkr83b9AHpemk1d9WmkI8s+AfdEXqbjYfZnh0GGA92fKCeMly6EV 8YxSK/NDu+2Y7Zz69tSpgrNhpp6oNep7vFrdsVlSb9UKHElKrFEvrr8knm8blUnISWIS Ygjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Ymbi2nILZkkoT/1mZ1CzBGJgr7G8IVgqfMmb2j5OZeM=; b=vhP2YKsls2lmLWNDf/NMJOZQVXUvws5G04FaK7VeKtgtw3wJv0oilwDfFj98R/pfMA ImxcDzAPfj8+6d0Y9QVL9eLO9bSrYwIRbj2zAwz5dvG4z1z+ctQnEQNPfDw/QiZJsYyz VPmYu144cNQJm01FvsrvvscBjQQcLtpYlFTfC7D5kujsuqTl35NyVfjOnibAiUrb5+s0 XzbflaSxwyXDjwMmKUvxNUa2M1+Lbr/wEQMeBiY+9QhcPgKYqejqDxy3QVhoufNHzAPE xN2RIXcc0HSc+jtPqLK8P0hA3VeEMpZWOVv+eJn8h7eBznfZC38+br0W4pYRTc0rswU1 /ivw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c5si2571475pga.119.2017.05.05.12.50.06; Fri, 05 May 2017 12:50:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755916AbdEETsy (ORCPT + 6 others); Fri, 5 May 2017 15:48:54 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:49709 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755568AbdEETsi (ORCPT ); Fri, 5 May 2017 15:48:38 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.129]) with ESMTPA (Nemesis) id 0Lghtu-1dsRu643Fe-00oI0Z; Fri, 05 May 2017 21:48:37 +0200 From: Arnd Bergmann To: Ben Hutchings Cc: stable@vger.kernel.org, Ralf Baechle , Arnd Bergmann Subject: [PATCH 3.16-stable 81/87] MIPS: DEC: Avoid la pseudo-instruction in delay slots Date: Fri, 5 May 2017 21:47:39 +0200 Message-Id: <20170505194745.3627137-82-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170505194745.3627137-1-arnd@arndb.de> References: <20170505194745.3627137-1-arnd@arndb.de> X-Provags-ID: V03:K0:km1VyVakeCp6Kln75davTDilAuYCXLZ9ZqewBVTUc0tHaMiUp4A 9KNGUp5rVJY8nfNMPikMmoZ/bQMGzxutIMA/ROE7hE5rjoYX4VFWGZbMyq/2xkOUbRQ7GzB j9ssrPezBEzjHGHDwgvs7mejmAZ1RdOrqwbY9t2Zn/CyOjjeqSMpwotb2W//9A9NHWngzbb ExfyQMHnLJiaUAUkLxHOg== X-UI-Out-Filterresults: notjunk:1; V01:K0:Efk3swj22QU=:Zru9CbAXshXZsDUJPCbXHD 3nwM2zjwBa/4EajTn7LwJBFUNqMksdElKSQQllmQmOZ69/2yzuoNznIWmjSQBDnFqHdSEbwGe zCPIZ8qhC5zGdcaVUQOVz+qdZ413OoH7sj0y9vhMC0S3d2qybBsdgEVgGlyEO44Ka9tSEyqJX oHDjKiUT//UPw0KgUqOZzP2c8cQJehaGf+glWWRU6cZmdi4/MgVKr+LUUZ8hIPJ4/7eikM6OK WR/gxEgHSoio40hXV6PT6MBjruRy6sz4QsbrjG1NeMDKn5Iox5Xxh3Yx/job5ahefAZD+omp5 pdvHRo9mur3K/p2wzHcvL1qo+PQyrJCSQwugDhUTLxZbPBNoEbyBZ55q5T0opatrc6lLtphlw 3xVEiCvH1OkVd4I8mKJ0Xq1y6m612Uw0NB4i0D4x2oaNYHPt05jSIbm9yuafY5Xv4/HSXVEMD o6DhlqTeeVkLzUyNa30EQbWqRPbNpHeHfkIHVSSoMwXWMm/x1gt1bTjI0928oPRfeFqidnR+9 hb6hj/CyUeK/M9ChJYsOr3nP/faov0EkupLR3GHdcjMC7D9e3KTT/Y3dHexqTXjibGqLp4su3 Tk0CgAD4gkPzB80kStGCLrHOi9pBvSeQjV5gsp7xizEqyeUm2VHXrCjsj0+iG3MK9xFkPwKJc U2nib8/GFMvjseB5fDrSMRi0DYDQ1kzARtvVumO7Dtd+XFJmGkb18ritJW7Ubuq7d+00= Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Ralf Baechle Commit a4d7f14bd8d3316f847c3e0f7020dad95a8a648a upstream. When expanding the la or dla pseudo-instruction in a delay slot the GNU assembler will complain should the pseudo-instruction expand to multiple actual instructions, since only the first of them will be in the delay slot leading to the pseudo-instruction being only partially executed if the branch is taken. Use of PTR_LA in the dec int-handler.S leads to such warnings: arch/mips/dec/int-handler.S: Assembler messages: arch/mips/dec/int-handler.S:149: Warning: macro instruction expanded into multiple instructions in a branch delay slot arch/mips/dec/int-handler.S:198: Warning: macro instruction expanded into multiple instructions in a branch delay slot Avoid this by open coding the PTR_LA macros. Signed-off-by: Ralf Baechle Signed-off-by: Arnd Bergmann --- arch/mips/dec/int-handler.S | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) -- 2.9.0 diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S index 41a2fa1fa12e..c7953f2aca4f 100644 --- a/arch/mips/dec/int-handler.S +++ b/arch/mips/dec/int-handler.S @@ -146,7 +146,25 @@ /* * Find irq with highest priority */ - PTR_LA t1,cpu_mask_nr_tbl + # open coded PTR_LA t1, cpu_mask_nr_tbl +#if (_MIPS_SZPTR == 32) + # open coded la t1, cpu_mask_nr_tbl + lui t1, %hi(cpu_mask_nr_tbl) + addiu t1, %lo(cpu_mask_nr_tbl) + +#endif +#if (_MIPS_SZPTR == 64) + # open coded dla t1, cpu_mask_nr_tbl + .set push + .set noat + lui t1, %highest(cpu_mask_nr_tbl) + lui AT, %hi(cpu_mask_nr_tbl) + daddiu t1, t1, %higher(cpu_mask_nr_tbl) + daddiu AT, AT, %lo(cpu_mask_nr_tbl) + dsll t1, 32 + daddu t1, t1, AT + .set pop +#endif 1: lw t2,(t1) nop and t2,t0 @@ -195,7 +213,25 @@ /* * Find irq with highest priority */ - PTR_LA t1,asic_mask_nr_tbl + # open coded PTR_LA t1,asic_mask_nr_tbl +#if (_MIPS_SZPTR == 32) + # open coded la t1, asic_mask_nr_tbl + lui t1, %hi(asic_mask_nr_tbl) + addiu t1, %lo(asic_mask_nr_tbl) + +#endif +#if (_MIPS_SZPTR == 64) + # open coded dla t1, asic_mask_nr_tbl + .set push + .set noat + lui t1, %highest(asic_mask_nr_tbl) + lui AT, %hi(asic_mask_nr_tbl) + daddiu t1, t1, %higher(asic_mask_nr_tbl) + daddiu AT, AT, %lo(asic_mask_nr_tbl) + dsll t1, 32 + daddu t1, t1, AT + .set pop +#endif 2: lw t2,(t1) nop and t2,t0