| Message ID | 20170508195541.1301420-1-arnd@arndb.de |
|---|---|
| State | Superseded |
| Headers | show |
On Mon, May 8, 2017 at 9:55 PM, Arnd Bergmann <arnd@arndb.de> wrote: > From: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > Commit 5008efc83bf85b647aa1cbc44718b1675bbb7444 upstream. > > The PJ4 inline asm sequence to write to cp15 cannot be built in Thumb-2 > mode, due to the way it performs arithmetic on the program counter, so it > is built in ARM mode instead. However, building C files in ARM mode under > CONFIG_THUMB2_KERNEL is problematic, since the instrumentation performed > by subsystems like ftrace does not expect having to deal with interworking > branches. > > Since the sequence in question is simply a poor man's ISB instruction, > let's use a straight 'isb' instead when building in Thumb2 mode. Thumb2 > implies V7, so 'isb' should always be supported in that case. > > Acked-by: Arnd Bergmann <arnd@arndb.de> > Acked-by: Nicolas Pitre <nico@linaro.org> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > --- > Hi Greg, > > As Ard pointed out, commit 13d1b9575ac2c2da ("ARM: 8221/1: PJ4: allow > building in Thumb-2 mode") which I suggested for backports into > 3.16 is broken unless we also take this one. > > I checked the other stable branches and found that both 3.18 and > 4.4 contain only the first of the two, so please apply this one on > both branches as well. Clarification: please apply this patch from email on 3.18.y and cherry-pick the original 5008efc83bf85b6 on 4.4.y to avoid rebasing yourself. Arnd
On Mon, May 08, 2017 at 09:57:54PM +0200, Arnd Bergmann wrote: > On Mon, May 8, 2017 at 9:55 PM, Arnd Bergmann <arnd@arndb.de> wrote: > > From: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > > > Commit 5008efc83bf85b647aa1cbc44718b1675bbb7444 upstream. > > > > The PJ4 inline asm sequence to write to cp15 cannot be built in Thumb-2 > > mode, due to the way it performs arithmetic on the program counter, so it > > is built in ARM mode instead. However, building C files in ARM mode under > > CONFIG_THUMB2_KERNEL is problematic, since the instrumentation performed > > by subsystems like ftrace does not expect having to deal with interworking > > branches. > > > > Since the sequence in question is simply a poor man's ISB instruction, > > let's use a straight 'isb' instead when building in Thumb2 mode. Thumb2 > > implies V7, so 'isb' should always be supported in that case. > > > > Acked-by: Arnd Bergmann <arnd@arndb.de> > > Acked-by: Nicolas Pitre <nico@linaro.org> > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > > --- > > Hi Greg, > > > > As Ard pointed out, commit 13d1b9575ac2c2da ("ARM: 8221/1: PJ4: allow > > building in Thumb-2 mode") which I suggested for backports into > > 3.16 is broken unless we also take this one. > > > > I checked the other stable branches and found that both 3.18 and > > 4.4 contain only the first of the two, so please apply this one on > > both branches as well. > > Clarification: please apply this patch from email on 3.18.y and > cherry-pick the original 5008efc83bf85b6 on 4.4.y to avoid > rebasing yourself. Now queued up this way, thanks. greg k-h
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 2ecc7d15bc09..03120e656aea 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -84,7 +84,6 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o -CFLAGS_pj4-cp0.o := -marm AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c index 8153e36b2491..7c9248b74d3f 100644 --- a/arch/arm/kernel/pj4-cp0.c +++ b/arch/arm/kernel/pj4-cp0.c @@ -66,9 +66,13 @@ static void __init pj4_cp_access_write(u32 value) __asm__ __volatile__ ( "mcr p15, 0, %1, c1, c0, 2\n\t" +#ifdef CONFIG_THUMB2_KERNEL + "isb\n\t" +#else "mrc p15, 0, %0, c1, c0, 2\n\t" "mov %0, %0\n\t" "sub pc, pc, #4\n\t" +#endif : "=r" (temp) : "r" (value)); }