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[209.132.180.67]) by mx.google.com with ESMTP id h13si12805392pgn.51.2017.05.09.03.05.24; Tue, 09 May 2017 03:05:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752155AbdEIKFY (ORCPT + 6 others); Tue, 9 May 2017 06:05:24 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:52272 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752009AbdEIKFX (ORCPT ); Tue, 9 May 2017 06:05:23 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue004 [212.227.15.129]) with ESMTPA (Nemesis) id 0LgtFa-1dn9nV1ifW-00oGjG; Tue, 09 May 2017 12:05:19 +0200 From: Arnd Bergmann To: Ben Hutchings Cc: stable@vger.kernel.org, Ard Biesheuvel , Russell King , Arnd Bergmann Subject: [PATCH 3.16-stable 14/14] ARM: 8452/3: PJ4: make coprocessor access sequences buildable in Thumb2 mode Date: Tue, 9 May 2017 12:05:02 +0200 Message-Id: <20170509100502.1358298-15-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170509100502.1358298-1-arnd@arndb.de> References: <20170509100502.1358298-1-arnd@arndb.de> X-Provags-ID: V03:K0:wrSpweiEKX7Wb4pE/kgwv3wZPL/Ho9Ant6tFRQjFLvZw9TMN4AR DNGlfM0i+zIGD4nkUi2vebg9sVn/88NiqLjmmywvcnkeU/5fgi6yENk7+P1EgwmprPFl0yJ FeWYDrf/GUuYd3VKjSol+rJ7soeSl4GqWMl4wQPBCpXPmG7l70CNP56iLwftWATPPILIIhx TNdMDpmTLZa95maNO9wPg== X-UI-Out-Filterresults: notjunk:1; V01:K0:7jfCCZfkCVI=:CAVpU2R7mCFSJBM92XEiUi h7Hn8XyohgLGfmzJhhhQFzq6GY/zCz8OLGWnELjOTKrAfvS4iYt7JqgQg9bVFzpZZaAWycWvb hQLbA4rjKEISCa7BLk/vlNxAL5Iyjc9iW7cjFdy1WhlDDfS6jLmsziwo6hPaHtT4hpx9YEzwS YREBOrqGokv5KzsXuZD0uG43vPMbEGgcULUYj8E31bwtwmr30mOWWdq5aXd2nnuSpuGQh2zFO PlZwceHWlwLsso+fK5WffTX95hDAi273wLqijiTtIXBpuSydUeXs50/9woGWxMOPGSIa3/R4h 2WJEiqKpdEkIxD6RA+4TmuaW4E2JmN/CRaJVPnDWBNMpn2dpRp0NK2/AW2sHdqRDofUY731z2 SHTCf29qzWPJLI+tuy7G+xr1v3tl2LjUxsEcDD9tpDy3oT5vm/ReoWeAADQhyMJ7MFL4jXBoJ qo16TLkc0onB4iIJptFVsWNy1ylWLxy5Eyu4WWzEzI5aSMZhe+jiEIr6Lk6lScwoRh/BEeAfa 6ycJMZ68Vu7p6ejYiqYymZ5GT/ZtYxYPKrbG1l31aiVTFPmD9I+4iFKFqkuagwbTvVN69mHTH 668r++0eSjS9FWe2D5GbGsI5B5Y0ht3UehBcmR5+NR4fXlPykmREDLA4LJk8aN43QCvCWQ+XH 8pil6IUxDmya7r/rVDuGfloKOUm0kC+PtPY2UIOuz6ZYMcivGIUs3zu8GHMYidvBc0gI= Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Ard Biesheuvel Commit 5008efc83bf85b647aa1cbc44718b1675bbb7444 upstream. The PJ4 inline asm sequence to write to cp15 cannot be built in Thumb-2 mode, due to the way it performs arithmetic on the program counter, so it is built in ARM mode instead. However, building C files in ARM mode under CONFIG_THUMB2_KERNEL is problematic, since the instrumentation performed by subsystems like ftrace does not expect having to deal with interworking branches. Since the sequence in question is simply a poor man's ISB instruction, let's use a straight 'isb' instead when building in Thumb2 mode. Thumb2 implies V7, so 'isb' should always be supported in that case. Acked-by: Arnd Bergmann Acked-by: Nicolas Pitre Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King Signed-off-by: Arnd Bergmann --- arch/arm/kernel/Makefile | 1 - arch/arm/kernel/pj4-cp0.c | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.9.0 diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 2ecc7d15bc09..03120e656aea 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -84,7 +84,6 @@ obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o -CFLAGS_pj4-cp0.o := -marm AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c index 8153e36b2491..7c9248b74d3f 100644 --- a/arch/arm/kernel/pj4-cp0.c +++ b/arch/arm/kernel/pj4-cp0.c @@ -66,9 +66,13 @@ static void __init pj4_cp_access_write(u32 value) __asm__ __volatile__ ( "mcr p15, 0, %1, c1, c0, 2\n\t" +#ifdef CONFIG_THUMB2_KERNEL + "isb\n\t" +#else "mrc p15, 0, %0, c1, c0, 2\n\t" "mov %0, %0\n\t" "sub pc, pc, #4\n\t" +#endif : "=r" (temp) : "r" (value)); }