From patchwork Mon May 15 06:50:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 99775 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp1411324qge; Sun, 14 May 2017 23:51:21 -0700 (PDT) X-Received: by 10.99.101.67 with SMTP id z64mr4685830pgb.78.1494831080947; Sun, 14 May 2017 23:51:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1494831080; cv=none; d=google.com; s=arc-20160816; b=k+cltubZo27sft1jlYpRKs+c3DoyLjmh3WQOnZhtV4lhG4p0E2dB4ChLYjABajk3/t Fy84eTqHrb3GpCOqV62fv/HCTOUgqawOc/Y4xa/XlArYKYDt7lr36IBhtXTipXMo2hgC UQSVu/ZjZs/7BQ5c22Bi3vnzUrseGjmPBZtRQssyORFsxQ9AZNHpwpH6/otwDpzlLYNA KAePCdDJ2xhPWQCAl0jcti5PASo89RQv1nNQRGwVDWd81sgEkyWtcBBn2NjqQL9vaE59 6/fJO9K1wlwAzcPr7kMOYMsT8ozJxIyjYXo1iKSVB+DoqW7zS93nvrdONVtR3qXdFLMg Zctw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=DPgS26iVjRbg6gHll8QOYDln/06j7pIPfBkBssfhZ+s=; b=FMOoqmYTzM19AemLrQFuWtmd8sRzvZTcyXSnKBHiRMIdMR7UlLNh0vXQm5cgkg2gml h1SK/3hBgwXP4wggBNOdT19bUBNbL6chpBxPiDHpT3jz2RHDToHaPdptFAz8l7lAPPD7 WRj55uFnOfTqpg6/oBhvscZfAL5FTLzFmqPdrng/ENPbsz8JXTI12BVZLaUx6x0MFTE5 DDJykI9MlplYOhTjko9GVUBoU+MrGSnWMYwroDHMkUXCpJFaM1rcWmB2tERk8WHtKUiQ 4WbfTh+wgkjuYhJ7KwbfrYaAB6nDYPagR41xtRIQOypc8h9Hm/QWQVrJ97ZQWLpYc7yV KWFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y17si9917185pfa.75.2017.05.14.23.51.20; Sun, 14 May 2017 23:51:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=samsung.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932648AbdEOGvT (ORCPT + 4 others); Mon, 15 May 2017 02:51:19 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:26309 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932651AbdEOGvP (ORCPT ); Mon, 15 May 2017 02:51:15 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OPZ007N6F1CDN40@mailout2.w1.samsung.com>; Mon, 15 May 2017 07:51:12 +0100 (BST) Received: from eusmges3.samsung.com (unknown [203.254.199.242]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170515065111eucas1p16464f66691158c729b0100ba6ebf4bb4~_tPCa0t2a1699416994eucas1p15; Mon, 15 May 2017 06:51:11 +0000 (GMT) Received: from eucas1p2.samsung.com ( [182.198.249.207]) by eusmges3.samsung.com (EUCPMTA) with SMTP id 1B.CC.17464.FDF49195; Mon, 15 May 2017 07:51:11 +0100 (BST) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55~_tPBqvdze1463014630eucas1p2V; Mon, 15 May 2017 06:51:11 +0000 (GMT) X-AuditID: cbfec7f2-f797e6d000004438-c5-59194fdfaa7a Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id E0.31.20206.5FF49195; Mon, 15 May 2017 07:51:33 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OPZ00GNMF0XY210@eusync2.samsung.com>; Mon, 15 May 2017 07:51:00 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Stephen Boyd , Michael Turquette , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 4/6] clk: samsung: exynos-audss: Convert to the new clk_hw API Date: Mon, 15 May 2017 08:50:47 +0200 Message-id: <1494831047-10235-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1493016143-21569-5-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrEIsWRmVeSWpSXmKPExsWy7djP87r3/SUjDbZNV7DYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbnHxlKvF4TftrBY/znSzOHB6vL/Ryu5xua+XyWPTqk42 j74tqxg9Pm+SC2CN4rJJSc3JLEst0rdL4MqYvfM+S0GvScWJuxvYGhhna3cxcnJICJhIzJ37 nQnCFpO4cG89WxcjF4eQwFJGiSm7zrBDOJ8ZJe619zHBdJzaNJMJIrGMUeJ8w02olgYmiaUn trCAVLEJGEp0ve1iA7FFBBwkPn96zQhSxCywk0liws+VYAlhgWCJq3umgI1lEVCVWHf2JiuI zSvgIfFq226odXISJ49NBotzCnhKTN6xkxVkkITAbzaJM5dagA7kAHJkJTYdYIaod5F4NBNi sYSAsMSr41vYIWwZicuTu1kg7H5GiaZWaADMYJQ495YXwraWOHz8ItguZgE+iUnbpjNDjOeV 6GgTgijxkDh55gnUVkeJrfd1IX6fwyjx4tUrxgmMMgsYGVYxiqSWFuempxYb6xUn5haX5qXr JefnbmIExvTpf8c/7WD8esLqEKMAB6MSD2/CZYlIIdbEsuLK3EOMEhzMSiK8hQ6SkUK8KYmV ValF+fFFpTmpxYcYpTlYlMR5uU5dixASSE8sSc1OTS1ILYLJMnFwSjUwBm2X+BC3To3FyZ2n Im9B4fdgGfHtb7STFt36U1s0i+1v2Fwn1aXT1yrPWbCELe6B0yTPQrfopRNL3NR2aK9qCd7x O61xy0x+o0t+W927cpTFV6+OTJ5z0l7idkDrvve7L26W3sbTtOmtyb4gkbOWBq4Vj0o4f9tM K+AWbJo8YYZLQuej53mxSizFGYmGWsxFxYkACIOdpOUCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMLMWRmVeSWpSXmKPExsVy+t/xK7pf/SUjDX5cN7TYOGM9q8X1L89Z Lc6f38Bu8bHnHqvFjPP7mCzWHrnLbnHxlKvF4TftrBY/znSzOHB6vL/Ryu5xua+XyWPTqk42 j74tqxg9Pm+SC2CNcrPJSE1MSS1SSM1Lzk/JzEu3VQoNcdO1UFLIS8xNtVWK0PUNCVJSKEvM KQXyjAzQgINzgHuwkr5dglvG7J33WQp6TSpO3N3A1sA4W7uLkZNDQsBE4tSmmUwQtpjEhXvr 2boYuTiEBJYwSsxYfIwRwmlikjh5oAmsik3AUKLrbRcbiC0i4CDx+dNrsCJmgd1MEhdPPmYE SQgLBEtc+HABrIhFQFVi3dmbrCA2r4CHxKttu6HWyUmcPDYZLM4p4CkxecdOMFsIqKb/+mXG CYy8CxgZVjGKpJYW56bnFhvpFSfmFpfmpesl5+duYgQG+LZjP7fsYOx6F3yIUYCDUYmHN+Gy RKQQa2JZcWXuIUYJDmYlEd5CB8lIId6UxMqq1KL8+KLSnNTiQ4ymQEdNZJYSTc4HRl9eSbyh iaG5paGRsYWFuZGRkjjv1A9XwoUE0hNLUrNTUwtSi2D6mDg4pRoYZ76Ss8pc5NERt7Y0qujP 9FXFKs/n3dKZ9+Um91bjXxpvTwvL7eDIOfP45pMXB4JLomvln/BKHepbc8l5q+BbhtlnO/P2 dahvNUya+GPj9te+f7jZO3I1Z366P32uGqfWLt+dU32DOS8yzD9oeOW9to+5UPdlzUOsRd/n 3albHV7kw6bbr6HWo8RSnJFoqMVcVJwIADWHq3SGAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55 X-RootMTR: 20170515065111eucas1p2127c41dc0fa0d069d5f09bc222f5bd55 References: <1493016143-21569-5-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Clock providers should use the new struct clk_hw based API, so convert Exynos Audio Subsystem clock provider to the new approach. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- Sylwester, if possible, please replace v2 with this fixed version in your tree, as it has not been merged yet to clk-next nor to linux-next. Changelog v3: - fixed clock data parameter passed to of_clk_add_hw_provider() - after conversion clk_data is a pointer, so passing it as &clk_data is wrong and causes serious issues --- drivers/clk/samsung/clk-exynos-audss.c | 57 +++++++++++++++++----------------- 1 file changed, 29 insertions(+), 28 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index cb7df358a27d..85edeb738853 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -22,9 +22,8 @@ #include static DEFINE_SPINLOCK(lock); -static struct clk **clk_table; static void __iomem *reg_base; -static struct clk_onecell_data clk_data; +static struct clk_hw_onecell_data *clk_data; /* * On Exynos5420 this will be a clock which has to be enabled before any * access to audss registers. Typically a child of EPLL. @@ -110,18 +109,18 @@ static void exynos_audss_clk_teardown(void) int i; for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) { - if (!IS_ERR(clk_table[i])) - clk_unregister_mux(clk_table[i]); + if (!IS_ERR(clk_data->hws[i])) + clk_hw_unregister_mux(clk_data->hws[i]); } for (; i < EXYNOS_SRP_CLK; i++) { - if (!IS_ERR(clk_table[i])) - clk_unregister_divider(clk_table[i]); + if (!IS_ERR(clk_data->hws[i])) + clk_hw_unregister_divider(clk_data->hws[i]); } - for (; i < clk_data.clk_num; i++) { - if (!IS_ERR(clk_table[i])) - clk_unregister_gate(clk_table[i]); + for (; i < clk_data->num; i++) { + if (!IS_ERR(clk_data->hws[i])) + clk_hw_unregister_gate(clk_data->hws[i]); } } @@ -133,6 +132,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *sclk_pcm_p = "sclk_pcm0"; struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; const struct exynos_audss_clk_drvdata *variant; + struct clk_hw **clk_table; struct resource *res; int i, ret = 0; @@ -149,14 +149,15 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) epll = ERR_PTR(-ENODEV); - clk_table = devm_kzalloc(&pdev->dev, - sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS, + clk_data = devm_kzalloc(&pdev->dev, + sizeof(*clk_data) + + sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS, GFP_KERNEL); - if (!clk_table) + if (!clk_data) return -ENOMEM; - clk_data.clks = clk_table; - clk_data.clk_num = variant->num_clks; + clk_data->num = variant->num_clks; + clk_table = clk_data->hws; pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); pll_in = devm_clk_get(&pdev->dev, "pll_in"); @@ -176,7 +177,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } } } - clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", + clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); @@ -187,53 +188,53 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) mout_i2s_p[1] = __clk_get_name(cdclk); if (!IS_ERR(sclk_audio)) mout_i2s_p[2] = __clk_get_name(sclk_audio); - clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", + clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); - clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", + clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp", "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); - clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL, + clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, "dout_aud_bus", "dout_srp", 0, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); - clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s", + clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s", "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, &lock); - clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk", + clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 0, 0, &lock); - clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus", + clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus", "dout_aud_bus", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 2, 0, &lock); - clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s", + clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s", "dout_i2s", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 3, 0, &lock); - clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus", + clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus", "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); if (!IS_ERR(sclk_pcm_in)) sclk_pcm_p = __clk_get_name(sclk_pcm_in); - clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", + clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm", sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); if (variant->has_adma_clk) { - clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 9, 0, &lock); } - for (i = 0; i < clk_data.clk_num; i++) { + for (i = 0; i < clk_data->num; i++) { if (IS_ERR(clk_table[i])) { dev_err(&pdev->dev, "failed to register clock %d\n", i); ret = PTR_ERR(clk_table[i]); @@ -241,8 +242,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } } - ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, - &clk_data); + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, + clk_data); if (ret) { dev_err(&pdev->dev, "failed to add clock provider\n"); goto unregister;