[1/2] ARM: dts: add GSBI8 defines to the MSM8660 family

Message ID 20170515075012.3696-1-linus.walleij@linaro.org
State Accepted
Commit 5594207294fcbfe8e9fe86c81d1d8b88cb530e66
Headers show
Series
  • [1/2] ARM: dts: add GSBI8 defines to the MSM8660 family
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Commit Message

Linus Walleij May 15, 2017, 7:50 a.m.
This defines the memory location and interrupt used by the GSBI8
I2C adapter on the MSM8660 SoCs. We add it as "disabled" by
default so that boards using this I2C can enable it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

---
 arch/arm/boot/dts/qcom-msm8660.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

-- 
2.9.3

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Comments

Bjorn Andersson May 24, 2017, 10:19 p.m. | #1
On Mon 15 May 00:50 PDT 2017, Linus Walleij wrote:

> This defines the memory location and interrupt used by the GSBI8

> I2C adapter on the MSM8660 SoCs. We add it as "disabled" by

> default so that boards using this I2C can enable it.

> 


Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>


Regards,
Bjorn
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Stephen Boyd June 2, 2017, 10:02 p.m. | #2
On 05/15, Linus Walleij wrote:
> diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi

> index 747669a62aa8..a53c0f9970bd 100644

> --- a/arch/arm/boot/dts/qcom-msm8660.dtsi

> +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi

> @@ -107,6 +107,31 @@

>  			reg = <0x900000 0x4000>;

>  		};

>  

> +

> +		gsbi8: gsbi@19800000 {

> +			compatible = "qcom,gsbi-v1.0.0";

> +			cell-index = <12>;

> +			reg = <0x19800000 0x100>;

> +			clocks = <&gcc GSBI8_H_CLK>;

> +			clock-names = "iface";

> +			#address-cells = <1>;

> +			#size-cells = <1>;

> +			ranges;

> +

> +			syscon-tcsr = <&tcsr>;

> +

> +			gsbi8_i2c: i2c@19880000 {

> +				compatible = "qcom,i2c-qup-v1.1.1";

> +				reg = <0x19880000 0x1000>;

> +				interrupts = <0 161 IRQ_TYPE_NONE>;


				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>?

> +				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;


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Andy Gross June 6, 2017, 2:11 a.m. | #3
On Fri, Jun 02, 2017 at 03:02:23PM -0700, Stephen Boyd wrote:
> On 05/15, Linus Walleij wrote:

> > diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi

> > index 747669a62aa8..a53c0f9970bd 100644

> > --- a/arch/arm/boot/dts/qcom-msm8660.dtsi

> > +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi

> > @@ -107,6 +107,31 @@

> >  			reg = <0x900000 0x4000>;

> >  		};

> >  

> > +

> > +		gsbi8: gsbi@19800000 {

> > +			compatible = "qcom,gsbi-v1.0.0";

> > +			cell-index = <12>;

> > +			reg = <0x19800000 0x100>;

> > +			clocks = <&gcc GSBI8_H_CLK>;

> > +			clock-names = "iface";

> > +			#address-cells = <1>;

> > +			#size-cells = <1>;

> > +			ranges;

> > +

> > +			syscon-tcsr = <&tcsr>;

> > +

> > +			gsbi8_i2c: i2c@19880000 {

> > +				compatible = "qcom,i2c-qup-v1.1.1";

> > +				reg = <0x19880000 0x1000>;

> > +				interrupts = <0 161 IRQ_TYPE_NONE>;

> 

> 				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>?


I'll fix this up.  No need for resend
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Patch

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 747669a62aa8..a53c0f9970bd 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -107,6 +107,31 @@ 
 			reg = <0x900000 0x4000>;
 		};
 
+
+		gsbi8: gsbi@19800000 {
+			compatible = "qcom,gsbi-v1.0.0";
+			cell-index = <12>;
+			reg = <0x19800000 0x100>;
+			clocks = <&gcc GSBI8_H_CLK>;
+			clock-names = "iface";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			syscon-tcsr = <&tcsr>;
+
+			gsbi8_i2c: i2c@19880000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x19880000 0x1000>;
+				interrupts = <0 161 IRQ_TYPE_NONE>;
+				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
+				clock-names = "core", "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		gsbi12: gsbi@19c00000 {
 			compatible = "qcom,gsbi-v1.0.0";
 			cell-index = <12>;