From patchwork Wed Apr 13 13:29:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 999 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:48:09 -0000 Delivered-To: patches@linaro.org Received: by 10.68.59.138 with SMTP id z10cs310012pbq; Wed, 13 Apr 2011 06:31:35 -0700 (PDT) Received: by 10.42.77.8 with SMTP id g8mr905817ick.478.1302701495432; Wed, 13 Apr 2011 06:31:35 -0700 (PDT) Received: from mail-iw0-f178.google.com (mail-iw0-f178.google.com [209.85.214.178]) by mx.google.com with ESMTPS id 13si1759325ibc.22.2011.04.13.06.31.35 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 13 Apr 2011 06:31:35 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=209.85.214.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: by iwn9 with SMTP id 9so1360764iwn.37 for ; Wed, 13 Apr 2011 06:31:35 -0700 (PDT) Received: by 10.42.151.133 with SMTP id e5mr2770680icw.178.1302701495167; Wed, 13 Apr 2011 06:31:35 -0700 (PDT) Received: from localhost.localdomain ([116.231.118.83]) by mx.google.com with ESMTPS id gx2sm442633ibb.43.2011.04.13.06.31.29 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 13 Apr 2011 06:31:34 -0700 (PDT) From: Jason Liu To: u-boot@lists.denx.de Cc: sbabic@denx.de Subject: [U-Boot][PATCH 2/2] MX53: loco: Add power init support Date: Wed, 13 Apr 2011 21:29:19 +0800 Message-Id: <1302701359-10996-3-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1302701359-10996-1-git-send-email-jason.hui@linaro.org> References: <1302701359-10996-1-git-send-email-jason.hui@linaro.org> Increase CPU core power to 1.25v via DA9053 PMIC, and after that CPU can ran to 1GHZ and DDR 400Mhz. Signed-off-by: Jason Liu --- arch/arm/include/asm/arch-mx5/sys_proto.h | 2 + board/freescale/mx53loco/mx53loco.c | 94 +++++++++++++++++++++++++++++ include/configs/mx53loco.h | 13 ++-- 3 files changed, 102 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 89ab8e8..9fc209d 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -29,5 +29,7 @@ u32 get_cpu_rev(void); void sdelay(unsigned long); void invalidate_dcache(u32); u32 get_device_type(void); +void pmic_reg_write(u32 reg, u32 value); +u32 pmic_reg_read(u32 reg); #endif diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index fd56c3d..9f15fa4 100755 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -28,12 +28,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -273,6 +275,93 @@ int board_mmc_init(bd_t *bis) } #endif +static void setup_i2c(unsigned int port_number) +{ + switch (port_number) { + case 0: + /* i2c1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* i2c1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + break; + case 1: + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX53_PIN_KEY_COL3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + break; + default: + printf("Warning: Wrong I2C port number\n"); + break; + } +} + +static void clock_init(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increase voltage to 1.25V, We can switch + * CPU clokc to 1Ghz and DDR to 400Mhz safely now + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (!ret) + printf("CPU: Switch CPU clock to 1GHZ OK\n"); + else + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (!ret) + printf("DDR: Switch DDR clock to 400MHz OK\n"); + else + printf("CPU: Switch DDR clock to 1GHZ failed\n"); +} + +static void power_init(void) +{ + unsigned int val; + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN; + val |= DA_BUCKCORE_VBCORE_1_250V; + pmic_reg_write(DA9053_BUCKCORE_REG, val); + val = pmic_reg_read(DA9053_SUPPLY_REG); + val |= DA9052_SUPPLY_VBCOREGO; + pmic_reg_write(DA9053_SUPPLY_REG, val); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -286,6 +375,11 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_MX53_LOCO; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; +#ifdef CONFIG_I2C_MXC + setup_i2c(0); + power_init(); + clock_init(); +#endif return 0; } diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 1e60335..ad94c31 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -47,17 +47,16 @@ #define CONFIG_SYS_MX53_UART1 /* I2C Configs */ -#define CONFIG_CMD_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MXC 1 -#define CONFIG_SYS_I2C_MX53_PORT2 1 +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe /* PMIC Configs */ -#define CONFIG_FSL_PMIC -#define CONFIG_FSL_PMIC_I2C -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 +#define CONFIG_DIALOG_PMIC +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 /* MMC Configs */ #define CONFIG_FSL_ESDHC