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[54.225.227.206]) by mx.google.com with ESMTP id l13si2044917qkh.140.2017.09.20.07.55.57; Wed, 20 Sep 2017 07:55:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B1A9060C95; Wed, 20 Sep 2017 14:55:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 8AB0560B2B; Wed, 20 Sep 2017 14:55:51 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 566C9609D1; Wed, 20 Sep 2017 14:55:48 +0000 (UTC) Received: from mail-pf0-f169.google.com (mail-pf0-f169.google.com [209.85.192.169]) by lists.linaro.org (Postfix) with ESMTPS id 30559608B3 for ; Wed, 20 Sep 2017 14:55:46 +0000 (UTC) Received: by mail-pf0-f169.google.com with SMTP id y29so1656614pff.0 for ; Wed, 20 Sep 2017 07:55:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ckZ7iyyD6kukcgxkkx6sATdzsZyCbdhm5xeaIq2tDWM=; b=DVLW69tf+d4TNrOFOJQtR1+Ue6pZyzBoPU0wDmHHYqfzr0vSK34abIyOhNioY5hlAC eEZY8+NXTcGbFvsbguLkIBE1i0/m6PPKfUa+Y1tvxH2zAVPNSDAHH4TgPv3pFKbJY1x2 Ir3RzvNTTh7yCdFXvUo08MjV3ov07Jhtc74eueI8+46eU6q7JyiyrZROI7i0VCH+3DnE k/2nsKJQQs5Jx1DojiRx5kNZeWub7RcBl7QQyKyPed5NsRGzNoAc8QSCcGSDogqrgJRX gGTUfmYJjnybgeEpeSvcCYz3pD7vznLgzb25PCxmUDis1fYeJHq6u4oRj188flsDuuGO 3Chg== X-Gm-Message-State: AHPjjUi2kmHP+WttpkE0OZQb+JvLQAkCrBCH3J0SH8Gpyxb3fz/aQ5Cv oOFjp0DqBXbNKtsQhlTCpP9N3C18 X-Google-Smtp-Source: AOwi7QBUZzbeaQI20Doe+VWHpvAYmtqLqCjUv24jBWM28eL3h88zKQZifsTG8gZzFPCm/h9kGKY6kg== X-Received: by 10.159.207.139 with SMTP id z11mr2313677plo.335.1505919345384; Wed, 20 Sep 2017 07:55:45 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id c7sm9157624pfc.55.2017.09.20.07.55.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Sep 2017 07:55:44 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Wed, 20 Sep 2017 22:48:44 +0800 Message-Id: <1505918938-52550-1-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v2 00/11] Update D03/D05 binary for edk2 update and bug fix. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1710-platforms-v2 rp-1710-osi-v2 Note: If occurs BIOS boot hang up issue, please revert below commit to fix: "2f03dc8" Chenhui Sun (1): Hisilicon/D03: remove the implemention of PerfTuning Heyi Guo (3): Hisilicon/D05: update all binary for update edk2 Hisilicon/D03: update all binary for update edk2 Hisilicon: Fix the drivers use the same GUID issue Ming Huang (4): Hisilicon D03/D05: get firmware version from FIRMWARE_VER D05/ACPI: Disable D05 SAS0 and SAS2 D05/ACPI: Modify I2C device Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. huangming (3): Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase D05/PCIe: Modify PcieRegionBase of secondary chip Hisilicon/D05/Pcie: fix bug of size definition .../D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +- .../Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +- .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- .../D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +- Platform/Hisilicon/D03/D03.dsc | 12 ++- Platform/Hisilicon/D03/D03.fdf | 5 +- .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D05/D05.dsc | 83 ++++++++++---------- Platform/Hisilicon/D05/D05.fdf | 4 +- .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +- .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +- .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 30 ++++--- .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 4 + .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 91 +++++++++++++++++++++- .../Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 2 +- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +---- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++ .../DS3231RealTimeClockLib.inf | 2 +- .../Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +- 24 files changed, 194 insertions(+), 101 deletions(-)