From patchwork Thu Nov 10 13:52:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 81657 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp739819qge; Thu, 10 Nov 2016 06:03:38 -0800 (PST) X-Received: by 10.200.56.228 with SMTP id g33mr5885930qtc.140.1478786618330; Thu, 10 Nov 2016 06:03:38 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id m76si3412231qkh.259.2016.11.10.06.03.38; Thu, 10 Nov 2016 06:03:38 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 06AAC60721; Thu, 10 Nov 2016 14:03:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A2AFB60E48; Thu, 10 Nov 2016 13:57:25 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2AAA760844; Thu, 10 Nov 2016 13:57:15 +0000 (UTC) Received: from mail-pf0-f181.google.com (mail-pf0-f181.google.com [209.85.192.181]) by lists.linaro.org (Postfix) with ESMTPS id DD5D360802 for ; Thu, 10 Nov 2016 13:53:36 +0000 (UTC) Received: by mail-pf0-f181.google.com with SMTP id i88so146366858pfk.2 for ; Thu, 10 Nov 2016 05:53:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wW+T7xr8Nf1Xa/At5YMYDiHko2K4cyorYjsvs/gqGUc=; b=gcBnlcpw9JgmcTuuWfDS6iwCwQQivS0SxXKaI90q3yYBKW98sni0SirKNCo8Aqo6RR 8qQaBCPrxzMocBZRJwR6vw4DnWqeGkBihNuihAxdwTKbaLpN+ThUcUDDlQ0HzKPmO1ge vKyLtXtCqGC2ASpuuDrHmC98pCQz3gtovZEZlGBR8ttuSLXbmRCAco7jnp2ylfHtvuUG N0427ZAyNH+ZMNB+XtK8QIkVYNh6GzY53kBqftuDA0zbVmSfM/3lGxvNAtAhHJ91eWUM VXj0sjzjitnSlPDtXtBQ2hlpCfKciH5S+Qlui91j6+SLwlErRj0hdQqzI65Ub0S14K+n zeGg== X-Gm-Message-State: ABUngvcYmfi04AOeSZy8QhnEXEYE1eMi0vGRAZWVkRPvmlJEAx9GxFNjxDPaaOXWeutv9TTg0Yo= X-Received: by 10.99.47.7 with SMTP id v7mr35985455pgv.15.1478786016154; Thu, 10 Nov 2016 05:53:36 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g78sm7625705pfe.19.2016.11.10.05.53.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Nov 2016 05:53:35 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 10 Nov 2016 21:52:11 +0800 Message-Id: <1478785950-24197-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> References: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 07/27] Hisilicon/I2CLib: Extend to support Hi1616 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Hi1616 has 10 I2C ports and the IP of I2C controller is DesignWare v2, which requires to write I2C_CMD_STOP bit (BIT9) for the last transfer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Include/Library/I2CLib.h | 2 +- Chips/Hisilicon/Library/I2CLib/I2CHw.h | 1 + Chips/Hisilicon/Library/I2CLib/I2CLib.c | 50 +++++++++----------------------- 3 files changed, 15 insertions(+), 38 deletions(-) diff --git a/Chips/Hisilicon/Include/Library/I2CLib.h b/Chips/Hisilicon/Include/Library/I2CLib.h index c3597f6..36e9f5f 100644 --- a/Chips/Hisilicon/Include/Library/I2CLib.h +++ b/Chips/Hisilicon/Include/Library/I2CLib.h @@ -33,7 +33,7 @@ typedef enum { }SPEED_MODE; -#define I2C_PORT_MAX 9 +#define I2C_PORT_MAX 10 diff --git a/Chips/Hisilicon/Library/I2CLib/I2CHw.h b/Chips/Hisilicon/Library/I2CLib/I2CHw.h index 0937997..aa561e9 100644 --- a/Chips/Hisilicon/Library/I2CLib/I2CHw.h +++ b/Chips/Hisilicon/Library/I2CLib/I2CHw.h @@ -26,6 +26,7 @@ #define I2C_TXRX_THRESHOLD 0x7 #define I2C_SS_SCLHCNT 0x493 #define I2C_SS_SCLLCNT 0x4fe +#define I2C_CMD_STOP_BIT BIT9 #define I2C_REG_WRITE(reg,data) \ MmioWrite32 ((reg), (data)) diff --git a/Chips/Hisilicon/Library/I2CLib/I2CLib.c b/Chips/Hisilicon/Library/I2CLib/I2CLib.c index 087a4ba..b5b388d 100644 --- a/Chips/Hisilicon/Library/I2CLib/I2CLib.c +++ b/Chips/Hisilicon/Library/I2CLib/I2CLib.c @@ -360,7 +360,12 @@ I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf) ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port); } - I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++); + if (Idx < ulLength - 1) { + I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++)); + } else { + //Send command stop bit for the last transfer + I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT); + } } ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port); @@ -386,13 +391,10 @@ EFI_STATUS EFIAPI I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf) { - UINT32 ulCnt; - UINT16 usTotalLen = 0; UINT32 ulFifo; UINT32 ulTimes = 0; UINT8 I2CWAddr[2]; EFI_STATUS Status; - UINT32 BytesLeft; UINT32 Idx = 0; UINTN Base; @@ -441,42 +443,14 @@ I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf) ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port); } - usTotalLen = ulRxLen; - BytesLeft = usTotalLen; - - while(BytesLeft >= I2C_DRV_ONCE_READ_BYTES_NUM){ - - - for(ulCnt = 0; ulCnt < I2C_DRV_ONCE_READ_BYTES_NUM; ulCnt++) { + while (ulRxLen > 0) { + if (ulRxLen > 1) { I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL); + } else { + //Send command stop bit for the last transfer + I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT); } - - for(ulCnt = 0; ulCnt < I2C_DRV_ONCE_READ_BYTES_NUM; ulCnt++) { - ulTimes = 0; - do { - I2C_Delay(2); - - while(++ulTimes > I2C_READ_TIMEOUT) { - (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port); - return EFI_TIMEOUT; - } - ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port); - - }while(0 == ulFifo); - - I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]); - } - BytesLeft -= I2C_DRV_ONCE_READ_BYTES_NUM; - } - - - for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) { - I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL); - } - - - for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) { ulTimes = 0; do { I2C_Delay(2); @@ -489,6 +463,8 @@ I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf) }while(0 == ulFifo); I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]); + + ulRxLen --; } (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);