From patchwork Tue Dec 6 10:56:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 86769 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1959904qgi; Tue, 6 Dec 2016 03:15:53 -0800 (PST) X-Received: by 10.200.51.119 with SMTP id u52mr54652446qta.226.1481022953688; Tue, 06 Dec 2016 03:15:53 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id w128si11409614qkd.147.2016.12.06.03.15.53; Tue, 06 Dec 2016 03:15:53 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 56348609B1; Tue, 6 Dec 2016 11:15:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 57A4B608B7; Tue, 6 Dec 2016 11:04:20 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4C5B660B51; Tue, 6 Dec 2016 11:04:09 +0000 (UTC) Received: from mail-pg0-f52.google.com (mail-pg0-f52.google.com [74.125.83.52]) by lists.linaro.org (Postfix) with ESMTPS id 2762F60A1A for ; Tue, 6 Dec 2016 10:59:46 +0000 (UTC) Received: by mail-pg0-f52.google.com with SMTP id x23so148343262pgx.1 for ; Tue, 06 Dec 2016 02:59:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t5SrwFOhBKUyF2C7smeoFbHsCp1SjnHwJLegYDufqVc=; b=MLnv4isITMqmgqAp5oFQbGvXoIaivw9r56U9gYUuPuwZCjvfn/K8yTE/6o/qBh73ze X5j4BaUrYY+7iobE0a6bo9ZX6ODlVebL+t6H5iaioUaSrfFCnb8Umw16PPCk+baKPInW TpqXdM/7aUlrgxEpxM1cHU5b8WDsA0iM99q1XpmfphUVyxJLh/v9Qj288athNhx/zUZ5 W4c4Ziq49cbrRAvgosmsIBoQQnEThnvYQwGKjLrM4lKWNWuwh/+HT+Jvuhz/Ana84iNW eGWM7+hiLsJzZBFMtOJTKJKa3S0CgPhLlEC+PFdOQLkb5YfXNvTk15ubxk4acAwsjJCG /DXQ== X-Gm-Message-State: AKaTC01/anqCd7nhin4IhCjIGXy6Ugc31xjpS2eT1Hm4rIfu8OdhnFAzzn3vibQrJJAppUTnmJk= X-Received: by 10.84.157.74 with SMTP id u10mr135466109plu.153.1481021985465; Tue, 06 Dec 2016 02:59:45 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id x26sm6980952pge.24.2016.12.06.02.59.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Dec 2016 02:59:45 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 6 Dec 2016 18:56:54 +0800 Message-Id: <1481021828-59826-24-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481021828-59826-1-git-send-email-heyi.guo@linaro.org> References: <1481021828-59826-1-git-send-email-heyi.guo@linaro.org> Cc: sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v6 23/37] Hisilicon/SMBIOS: Update ProcessorID from MIDR X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" There is no register restore processor id at ARM Platform,we talked with ARM Charles and made a agreement that we can use MIDR instead,maybe there will be a specific register to read the processor id in future. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Charles Garcia-Tobin Reviewed-by: Leif Lindholm --- .../Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index 07dae5f..005d28f 100644 --- a/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -490,6 +490,7 @@ AddSmbiosProcessorTypeTable ( CHAR16 *CpuVersion; STRING_REF TokenToUpdate; + UINT64 *ProcessorId; Type4Record = NULL; ProcessorManuStr = NULL; ProcessorVersionStr = NULL; @@ -614,6 +615,8 @@ AddSmbiosProcessorTypeTable ( Type4Record->ProcessorCharacteristics = ProcessorCharacteristics.Data; Type4Record->ExternalClock = (UINT16)(ArmReadCntFrq() / 1000 / 1000); + ProcessorId = (UINT64 *)&(Type4Record->ProcessorId); + *ProcessorId = ArmReadMidr(); OptionalStrStart = (CHAR8 *) (Type4Record + 1); UnicodeStrToAsciiStr (ProcessorSocketStr, OptionalStrStart);