From patchwork Tue Apr 8 15:12:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 28011 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yh0-f70.google.com (mail-yh0-f70.google.com [209.85.213.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id AB31720447 for ; Tue, 8 Apr 2014 15:15:53 +0000 (UTC) Received: by mail-yh0-f70.google.com with SMTP id c41sf3216921yho.9 for ; Tue, 08 Apr 2014 08:15:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=wwqERvTgBFSunhqwoyZTYmU0mLSQTHNmXJVkfubFZT0=; b=GV0vWAGa9PDnU07cjNlhFm0dE6t9JOQ4YMi4CwZQvZnaRrg2GdF+jq4JlDF/e+VAiM PBFtI6pZnOvZUEECTPSBalO/l0zEh/qetiba8fXfNSPNyiMeyv3KSJVSDfzNXOGhZSXP 8bVa3ZQufLRlO/DobwjLbaJS38I88GGEIYzo9W58t66Q+CdgPqXIK29EfU7mgFhHGjK4 VcYqm+bF1/FA6UvM4FGqeSCo/lFR6mx4Xq12kU29lKRlTU4rhr1H+qPmrKogN91qQRG7 UAuHXKLHwcysJERXZ/XGw+dl3EXu3eZSHbB2hBw8FFody8B9cFkBHskSCFMqjYVDmQzv gj9w== X-Gm-Message-State: ALoCoQlGdjmgOeiV/s0el8L6/aQ7UIbJ5v7cmM9MJSwyNljTdC1uZfstkNz1vuustEtx+5EHqAmP X-Received: by 10.58.22.70 with SMTP id b6mr1792707vef.13.1396970152842; Tue, 08 Apr 2014 08:15:52 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.40.200 with SMTP id x66ls240351qgx.46.gmail; Tue, 08 Apr 2014 08:15:52 -0700 (PDT) X-Received: by 10.52.175.166 with SMTP id cb6mr3026650vdc.1.1396970152671; Tue, 08 Apr 2014 08:15:52 -0700 (PDT) Received: from mail-vc0-f178.google.com (mail-vc0-f178.google.com [209.85.220.178]) by mx.google.com with ESMTPS id tz5si446002vdc.133.2014.04.08.08.15.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 08:15:52 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.178; Received: by mail-vc0-f178.google.com with SMTP id im17so878697vcb.37 for ; Tue, 08 Apr 2014 08:15:52 -0700 (PDT) X-Received: by 10.52.33.136 with SMTP id r8mr3093897vdi.2.1396970152585; Tue, 08 Apr 2014 08:15:52 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp254090vcv; Tue, 8 Apr 2014 08:15:52 -0700 (PDT) X-Received: by 10.42.86.196 with SMTP id v4mr1851342icl.62.1396970151389; Tue, 08 Apr 2014 08:15:51 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id h1si3939016igy.1.2014.04.08.08.15.50 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 08 Apr 2014 08:15:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXih-0005OS-N3; Tue, 08 Apr 2014 15:13:51 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXif-0005KS-5o for xen-devel@lists.xensource.com; Tue, 08 Apr 2014 15:13:49 +0000 Received: from [193.109.254.147:51289] by server-3.bemta-14.messagelabs.com id 91/2A-22179-C2214435; Tue, 08 Apr 2014 15:13:48 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-3.tower-27.messagelabs.com!1396970024!7017602!3 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 12300 invoked from network); 8 Apr 2014 15:13:47 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-3.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 8 Apr 2014 15:13:47 -0000 X-IronPort-AV: E=Sophos;i="4.97,818,1389744000"; d="scan'208";a="117915017" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 08 Apr 2014 15:12:53 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Tue, 8 Apr 2014 11:12:52 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WXXhk-0005Ms-19; Tue, 08 Apr 2014 16:12:52 +0100 From: Stefano Stabellini To: Date: Tue, 8 Apr 2014 16:12:46 +0100 Message-ID: <1396969969-18973-9-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v7 09/12] xen/arm: second irq injection while the first irq is still inflight X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Set GICH_LR_PENDING in the corresponding GICH_LR to inject a second irq while the first one is still active. If the first irq is already pending (not active), just clear GIC_IRQ_GUEST_QUEUED because the irq has already been injected and is already visible by the guest. If the irq has already been EOI'ed then just clear the GICH_LR right away and move the interrupt to lr_pending so that it is going to be reinjected by gic_restore_pending_irqs on return to guest. If the target cpu is not the current cpu, then set GIC_IRQ_GUEST_QUEUED and send an SGI. The target cpu is going to be interrupted and call gic_clear_lrs, that is going to take the same actions. Unify the inflight and non-inflight code paths in vgic_vcpu_inject_irq. Do not call vgic_vcpu_inject_irq from gic_inject if evtchn_upcall_pending is set. If we remove that call, we don't need to special case evtchn_irq in vgic_vcpu_inject_irq anymore. We also need to force the first injection of evtchn_irq (call gic_vcpu_inject_irq) from vgic_enable_irqs because evtchn_upcall_pending is already set by common code on vcpu creation. Signed-off-by: Stefano Stabellini --- Changes in v7: - remove warning printk "Changing priority of an inflight interrupt is not supported". Changes in v3: - do not use the PENDING and ACTIVE state for HW interrupts; - unify the inflight and non-inflight code paths in vgic_vcpu_inject_irq. --- xen/arch/arm/gic.c | 37 ++++++++++++++++++++++++------------- xen/arch/arm/vgic.c | 30 +++++++++++++++--------------- 2 files changed, 39 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index bed6e9c..13ce703 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -680,6 +680,14 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, { int i; unsigned long flags; + struct pending_irq *n = irq_to_pending(v, virtual_irq); + + if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &n->status)) + { + if ( v == current ) + gic_update_one_lr(v, n->lr); + return; + } spin_lock_irqsave(&gic.lock, flags); @@ -705,20 +713,27 @@ static void gic_update_one_lr(struct vcpu *v, int i) struct pending_irq *p; uint32_t lr; int irq; - bool_t inflight; ASSERT(spin_is_locked(&v->arch.vgic.lock)); lr = GICH[GICH_LR + i]; - if ( !(lr & (GICH_LR_PENDING|GICH_LR_ACTIVE)) ) + irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK; + p = irq_to_pending(v, irq); + if ( lr & GICH_LR_ACTIVE ) { - inflight = 0; + /* HW interrupts cannot be ACTIVE and PENDING */ + if ( p->desc == NULL && + test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) + GICH[GICH_LR + i] = lr | GICH_LR_PENDING; + } else if ( lr & GICH_LR_PENDING ) { + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); + } else { + spin_lock(&gic.lock); + GICH[GICH_LR + i] = 0; clear_bit(i, &this_cpu(lr_mask)); - irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK; - spin_lock(&gic.lock); - p = irq_to_pending(v, irq); if ( p->desc != NULL ) p->desc->status &= ~IRQ_INPROGRESS; clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); @@ -726,12 +741,11 @@ static void gic_update_one_lr(struct vcpu *v, int i) if ( test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) { - inflight = 1; gic_raise_guest_irq(v, irq, p->priority); - } - spin_unlock(&gic.lock); - if ( !inflight ) + } else list_del_init(&p->inflight); + + spin_unlock(&gic.lock); } } @@ -791,9 +805,6 @@ int gic_events_need_delivery(void) void gic_inject(void) { - if ( vcpu_info(current, evtchn_upcall_pending) ) - vgic_vcpu_inject_irq(current, current->domain->arch.evtchn_irq); - gic_restore_pending_irqs(current); if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 6a89a1e..435a8d7 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -389,7 +389,11 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) irq = i + (32 * n); p = irq_to_pending(v, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); - if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + if ( irq == v->domain->arch.evtchn_irq && + vcpu_info(current, evtchn_upcall_pending) && + list_empty(&p->inflight) ) + vgic_vcpu_inject_irq(v, irq); + else if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) gic_raise_guest_irq(v, irq, p->priority); if ( p->desc != NULL ) p->desc->handler->enable(p->desc); @@ -696,14 +700,6 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) spin_lock_irqsave(&v->arch.vgic.lock, flags); - if ( !list_empty(&n->inflight) ) - { - if ( (irq != current->domain->arch.evtchn_irq) || - (!test_bit(GIC_IRQ_GUEST_VISIBLE, &n->status)) ) - set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); - goto out; - } - /* vcpu offline */ if ( test_bit(_VPF_down, &v->pause_flags) ) { @@ -715,21 +711,25 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) n->irq = irq; set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); - n->priority = priority; /* the irq is enabled */ if ( test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) gic_raise_guest_irq(v, irq, priority); - list_for_each_entry ( iter, &v->arch.vgic.inflight_irqs, inflight ) + if ( list_empty(&n->inflight) ) { - if ( iter->priority > priority ) + n->priority = priority; + list_for_each_entry ( iter, &v->arch.vgic.inflight_irqs, inflight ) { - list_add_tail(&n->inflight, &iter->inflight); - goto out; + if ( iter->priority > priority ) + { + list_add_tail(&n->inflight, &iter->inflight); + goto out; + } } + list_add_tail(&n->inflight, &v->arch.vgic.inflight_irqs); } - list_add_tail(&n->inflight, &v->arch.vgic.inflight_irqs); + out: spin_unlock_irqrestore(&v->arch.vgic.lock, flags); /* we have a new higher priority irq, inject it into the guest */