From patchwork Fri May 16 14:40:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 30334 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f69.google.com (mail-pa0-f69.google.com [209.85.220.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B5F4B20A25 for ; Fri, 16 May 2014 14:42:05 +0000 (UTC) Received: by mail-pa0-f69.google.com with SMTP id ey11sf13347719pad.0 for ; Fri, 16 May 2014 07:42:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=oMtPpOuY4S0d8wxHvoxMNKoYnZH2NLpk5BK+XMVP/7U=; b=hkgklUjfmXtZKvoCM4ELcjTFKIxEzXKymKbOjxHrjl/uwkiKl5/pt1H7aOSp/LSuQL jDriKZMdZFTxeK48mb2bVuKAEUHlUKhggkYoBs3GstCe1bXDYyJ8h+9ViV53M6algnLy ZPcN+bGjsmNgLGwD13T7K4QPl5i5FDxi+iPvLcQ0dO/RtkyX3U+91cseeibnBin+Kq/F Mj7QOQ1saJlQvgRijQiAH3ptt4WFn3mkgLg0qhsOuqryDi1jUJJvwDUnTLU2hgA+jFZR YMni6IcrK5EPk21cTSmn3cCMz2zkElmRtUUnev3A2F+0pde22MO+tc6dh4XsmbRzXdxJ EwpA== X-Gm-Message-State: ALoCoQl+mHT+nw9kDt98jIzUlNGW5f/UF17g4oW32zCXnBjMnXk2bqSEKmUJbf0SZxVFZGG3+3Mh X-Received: by 10.66.190.202 with SMTP id gs10mr8759048pac.0.1400251325068; Fri, 16 May 2014 07:42:05 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.97.99 with SMTP id l90ls730910qge.13.gmail; Fri, 16 May 2014 07:42:04 -0700 (PDT) X-Received: by 10.58.178.70 with SMTP id cw6mr1401354vec.24.1400251324903; Fri, 16 May 2014 07:42:04 -0700 (PDT) Received: from mail-ve0-f171.google.com (mail-ve0-f171.google.com [209.85.128.171]) by mx.google.com with ESMTPS id tx4si1630823vdc.94.2014.05.16.07.42.04 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 16 May 2014 07:42:04 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.171 as permitted sender) client-ip=209.85.128.171; Received: by mail-ve0-f171.google.com with SMTP id oz11so3230494veb.30 for ; Fri, 16 May 2014 07:42:04 -0700 (PDT) X-Received: by 10.58.198.107 with SMTP id jb11mr14646225vec.10.1400251324794; Fri, 16 May 2014 07:42:04 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp58339vcb; Fri, 16 May 2014 07:42:04 -0700 (PDT) X-Received: by 10.224.134.194 with SMTP id k2mr23551674qat.5.1400251323553; Fri, 16 May 2014 07:42:03 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id 11si4314240qgk.62.2014.05.16.07.42.03 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 16 May 2014 07:42:03 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WlJJR-0005Ln-Su; Fri, 16 May 2014 14:40:41 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WlJJQ-0005LY-1L for xen-devel@lists.xenproject.org; Fri, 16 May 2014 14:40:40 +0000 Received: from [85.158.137.68:27777] by server-14.bemta-3.messagelabs.com id F6/0F-30903-76326735; Fri, 16 May 2014 14:40:39 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-11.tower-31.messagelabs.com!1400251238!4354326!1 X-Originating-IP: [74.125.83.41] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 17105 invoked from network); 16 May 2014 14:40:38 -0000 Received: from mail-ee0-f41.google.com (HELO mail-ee0-f41.google.com) (74.125.83.41) by server-11.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 16 May 2014 14:40:38 -0000 Received: by mail-ee0-f41.google.com with SMTP id t10so1637802eei.14 for ; Fri, 16 May 2014 07:40:37 -0700 (PDT) X-Received: by 10.14.95.129 with SMTP id p1mr511827eef.102.1400251237819; Fri, 16 May 2014 07:40:37 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id s46sm20538730ees.3.2014.05.16.07.40.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 May 2014 07:40:36 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Fri, 16 May 2014 15:40:27 +0100 Message-Id: <1400251232-7695-2-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1400251232-7695-1-git-send-email-julien.grall@linaro.org> References: <1400251232-7695-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v7 1/6] xen/arm: IRQ: Store IRQ type in arch_irq_desc X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: For now, ARM uses different IRQ functions to setup an interrupt handler. This is a bit annoying for common driver because we have to add idefery when an IRQ is setup (see ns16550_init_postirq for an example). To avoid to completely fork the IRQ management code, we can introduce a field to store the IRQ type (e.g level/edge ...). This patch also adds platform_get_irq which will retrieve the IRQ from the device tree and setup correctly the IRQ type. In order to use this solution, we have to move init_IRQ earlier for the boot CPU. It's fine because the code only depends on percpu. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v7: - Rename irq_check_type into irq_validate_new_type - Rename irq_set_type into irq_set_spi_type Changes in v6: - Introduce DT_IRQ_TYPE_INVALID to initialize IRQ type - Introduce local_irqs_type to avoid use boot CPU PPIs type config. Will be usefull for hotplug - Export irq_set_type and restrict for SPIs - Split IRQ set type for PPIs in another function Changes in v5: - Update comment in init_local_irq_data - Don't set desc.arch.type on boot cpu in init_local_irq_data - Use new macro boot_cpu instead of percpu(myvar, 0) Changes in v4: - Add an ASSERT to check if irq_set_type hasn't failed for PPI on other CPU than 0 - platform_get_irq return -1 in case of error. Changes in v3: - irqflags is unsigned long not unsigned int - fix comment - don't need to set IRQ type when NONE is used (already set at startup). Changes in v2: - Patch added --- xen/arch/arm/gic.c | 25 +++++---- xen/arch/arm/irq.c | 125 ++++++++++++++++++++++++++++++++++++++--- xen/arch/arm/setup.c | 3 +- xen/include/asm-arm/gic.h | 5 +- xen/include/asm-arm/irq.h | 6 ++ xen/include/xen/device_tree.h | 3 + 6 files changed, 146 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 577d85b..13eeb33 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -216,14 +216,21 @@ static hw_irq_controller gic_guest_irq_type = { /* * - needs to be called with a valid cpu_mask, ie each cpu in the mask has * already called gic_cpu_init + * - desc.lock must be held + * - arch.type must be valid (i.e != DT_IRQ_TYPE_INVALID) */ -static void gic_set_irq_properties(unsigned int irq, bool_t level, +static void gic_set_irq_properties(struct irq_desc *desc, const cpumask_t *cpu_mask, unsigned int priority) { volatile unsigned char *bytereg; uint32_t cfg, edgebit; unsigned int mask; + unsigned int irq = desc->irq; + unsigned int type = desc->arch.type; + + ASSERT(type != DT_IRQ_TYPE_INVALID); + ASSERT(spin_is_locked(&desc->lock)); spin_lock(&gic.lock); @@ -232,9 +239,9 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, /* Set edge / level */ cfg = GICD[GICD_ICFGR + irq / 16]; edgebit = 2u << (2 * (irq % 16)); - if ( level ) + if ( type & DT_IRQ_TYPE_LEVEL_MASK ) cfg &= ~edgebit; - else + else if ( type & DT_IRQ_TYPE_EDGE_BOTH ) cfg |= edgebit; GICD[GICD_ICFGR + irq / 16] = cfg; @@ -252,8 +259,8 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, /* Program the GIC to route an interrupt to the host (i.e. Xen) * - needs to be called with desc.lock held */ -void gic_route_irq_to_xen(struct irq_desc *desc, bool_t level, - const cpumask_t *cpu_mask, unsigned int priority) +void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, + unsigned int priority) { ASSERT(priority <= 0xff); /* Only 8 bits of priority */ ASSERT(desc->irq < gic.lines);/* Can't route interrupts that don't exist */ @@ -262,15 +269,14 @@ void gic_route_irq_to_xen(struct irq_desc *desc, bool_t level, desc->handler = &gic_host_irq_type; - gic_set_irq_properties(desc->irq, level, cpu_mask, priority); + gic_set_irq_properties(desc, cpu_mask, priority); } /* Program the GIC to route an interrupt to a guest * - desc.lock must be held */ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc, - bool_t level, const cpumask_t *cpu_mask, - unsigned int priority) + const cpumask_t *cpu_mask, unsigned int priority) { struct pending_irq *p; ASSERT(spin_is_locked(&desc->lock)); @@ -278,8 +284,7 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc, desc->handler = &gic_guest_irq_type; desc->status |= IRQ_GUEST; - gic_set_irq_properties(desc->irq, level, cpumask_of(smp_processor_id()), - GIC_PRI_IRQ); + gic_set_irq_properties(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); /* TODO: do not assume delivery to vcpu0 */ p = irq_to_pending(d->vcpu[0], desc->irq); diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 44696e7..832ee90 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -27,6 +27,9 @@ #include +static unsigned int local_irqs_type[NR_LOCAL_IRQS]; +static DEFINE_SPINLOCK(local_irqs_type_lock); + static void ack_none(struct irq_desc *irq) { printk("unexpected IRQ trap at irq %02x\n", irq->irq); @@ -55,6 +58,7 @@ irq_desc_t *__irq_to_desc(int irq) int __init arch_init_one_irq_desc(struct irq_desc *desc) { + desc->arch.type = DT_IRQ_TYPE_INVALID; return 0; } @@ -77,18 +81,37 @@ static int __cpuinit init_local_irq_data(void) { int irq; + spin_lock(&local_irqs_type_lock); + for (irq = 0; irq < NR_LOCAL_IRQS; irq++) { struct irq_desc *desc = irq_to_desc(irq); init_one_irq_desc(desc); desc->irq = irq; desc->action = NULL; + + /* PPIs are included in local_irqs, we copy the IRQ type from + * local_irqs_type when bringing up local IRQ for this CPU in + * order to pick up any configuration done before this CPU came + * up. For interrupts configured after this point this is done in + * irq_set_type. + */ + desc->arch.type = local_irqs_type[irq]; } + spin_unlock(&local_irqs_type_lock); + return 0; } void __init init_IRQ(void) { + int irq; + + spin_lock(&local_irqs_type_lock); + for ( irq = 0; irq < NR_LOCAL_IRQS; irq++ ) + local_irqs_type[irq] = DT_IRQ_TYPE_INVALID; + spin_unlock(&local_irqs_type_lock); + BUG_ON(init_local_irq_data() < 0); BUG_ON(init_irq_data() < 0); } @@ -275,9 +298,6 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) /* First time the IRQ is setup */ if ( disabled ) { - bool_t level; - - level = dt_irq_is_level_triggered(irq); /* It's fine to use smp_processor_id() because: * For PPI: irq_desc is banked * For SPI: we don't care for now which CPU will receive the @@ -285,7 +305,8 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) * TODO: Handle case where SPI is setup on different CPU than * the targeted CPU and the priority. */ - gic_route_irq_to_xen(desc, level, cpumask_of(smp_processor_id()), + desc->arch.type = irq->type; + gic_route_irq_to_xen(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); desc->handler->startup(desc); } @@ -303,7 +324,6 @@ int route_dt_irq_to_guest(struct domain *d, const struct dt_irq *irq, struct irq_desc *desc = irq_to_desc(irq->irq); unsigned long flags; int retval = 0; - bool_t level; action = xmalloc(struct irqaction); if (!action) @@ -341,8 +361,8 @@ int route_dt_irq_to_guest(struct domain *d, const struct dt_irq *irq, if ( retval ) goto out; - level = dt_irq_is_level_triggered(irq); - gic_route_irq_to_guest(d, desc, level, cpumask_of(smp_processor_id()), + desc->arch.type = irq->type; + gic_route_irq_to_guest(d, desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); spin_unlock_irqrestore(&desc->lock, flags); return 0; @@ -383,6 +403,97 @@ void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) BUG(); } +static bool_t irq_validate_new_type(unsigned int curr, unsigned new) +{ + return (curr == DT_IRQ_TYPE_INVALID || curr == new ); +} + +int irq_set_spi_type(unsigned int spi, unsigned int type) +{ + unsigned long flags; + struct irq_desc *desc = irq_to_desc(spi); + int ret = -EBUSY; + + /* This function should not be used for other than SPIs */ + if ( spi < NR_LOCAL_IRQS ) + return -EINVAL; + + spin_lock_irqsave(&desc->lock, flags); + + if ( !irq_validate_new_type(desc->arch.type, type) ) + goto err; + + desc->arch.type = type; + + ret = 0; + +err: + spin_unlock_irqrestore(&desc->lock, flags); + return ret; +} + +static int irq_local_set_type(unsigned int irq, unsigned int type) +{ + unsigned int cpu; + unsigned int old_type; + unsigned long flags; + int ret = -EBUSY; + struct irq_desc *desc; + + ASSERT(irq < NR_LOCAL_IRQS); + + spin_lock(&local_irqs_type_lock); + + old_type = local_irqs_type[irq]; + + if ( !irq_validate_new_type(old_type, type) ) + goto unlock; + + ret = 0; + /* We don't need to reconfigure if the type is correctly set */ + if ( old_type == type ) + goto unlock; + + local_irqs_type[irq] = type; + + for_each_cpu( cpu, &cpu_online_map ) + { + desc = &per_cpu(local_irq_desc, cpu)[irq]; + spin_lock_irqsave(&desc->lock, flags); + desc->arch.type = type; + spin_unlock_irqrestore(&desc->lock, flags); + } + +unlock: + spin_unlock(&local_irqs_type_lock); + return ret; +} + +int platform_get_irq(const struct dt_device_node *device, int index) +{ + struct dt_irq dt_irq; + unsigned int type, irq; + int res; + + res = dt_device_get_irq(device, index, &dt_irq); + if ( res ) + return -1; + + irq = dt_irq.irq; + type = dt_irq.type; + + /* Setup the IRQ type */ + if ( irq < NR_LOCAL_IRQS ) + res = irq_local_set_type(irq, type); + else + res = irq_set_spi_type(irq, type); + + if ( res ) + return -1; + + return irq; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index c983d95..b9ce7a9 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -688,6 +688,8 @@ void __init start_xen(unsigned long boot_phys_offset, dt_unflatten_host_device_tree(); dt_irq_xlate = gic_irq_xlate; + init_IRQ(); + dt_uart_init(); console_init_preirq(); @@ -717,7 +719,6 @@ void __init start_xen(unsigned long boot_phys_offset, tasklet_subsys_init(); - init_IRQ(); xsm_dt_init(); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index b750b17..80f8dd2 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -168,11 +168,10 @@ extern void vgic_clear_pending_irqs(struct vcpu *v); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); /* Program the GIC to route an interrupt */ -extern void gic_route_irq_to_xen(struct irq_desc *desc, bool_t level, - const cpumask_t *cpu_mask, +extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, unsigned int priority); extern void gic_route_irq_to_guest(struct domain *, struct irq_desc *desc, - bool_t level, const cpumask_t *cpu_mask, + const cpumask_t *cpu_mask, unsigned int priority); extern void gic_inject(void); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index b52c26f..a7a796d 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -16,6 +16,7 @@ struct arch_pirq struct arch_irq_desc { int eoi_cpu; + unsigned int type; }; #define NR_LOCAL_IRQS 32 @@ -47,6 +48,11 @@ int setup_dt_irq(const struct dt_irq *irq, struct irqaction *new); int route_dt_irq_to_guest(struct domain *d, const struct dt_irq *irq, const char *devname); +/* Set IRQ type for an SPI */ +int irq_set_spi_type(unsigned int spi, unsigned int type); + +int platform_get_irq(const struct dt_device_node *device, int index); + #endif /* _ASM_HW_IRQ_H */ /* * Local variables: diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index a169f0d..25db076 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -135,6 +135,7 @@ struct dt_phandle_args { * DT_IRQ_TYPE_LEVEL_LOW - low level triggered * DT_IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits * DT_IRQ_TYPE_SENSE_MASK - Mask for all the above bits + * DT_IRQ_TYPE_INVALID - Use to initialize the type */ #define DT_IRQ_TYPE_NONE 0x00000000 #define DT_IRQ_TYPE_EDGE_RISING 0x00000001 @@ -147,6 +148,8 @@ struct dt_phandle_args { (DT_IRQ_TYPE_LEVEL_LOW | DT_IRQ_TYPE_LEVEL_HIGH) #define DT_IRQ_TYPE_SENSE_MASK 0x0000000f +#define DT_IRQ_TYPE_INVALID 0x00000010 + /** * dt_irq - describe an IRQ in the device tree * @irq: IRQ number