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[50.57.142.19]) by mx.google.com with ESMTPS id k19si8444509qaa.101.2014.06.10.07.23.00 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 10 Jun 2014 07:23:04 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WuMvi-0004H0-K9; Tue, 10 Jun 2014 14:21:38 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WuMvh-0004Go-4e for xen-devel@lists.xensource.com; Tue, 10 Jun 2014 14:21:37 +0000 Received: from [85.158.137.68:62018] by server-5.bemta-3.messagelabs.com id 64/A4-18761-07417935; Tue, 10 Jun 2014 14:21:36 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-7.tower-31.messagelabs.com!1402410093!9188916!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24728 invoked from network); 10 Jun 2014 14:21:35 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-7.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 10 Jun 2014 14:21:35 -0000 X-IronPort-AV: E=Sophos; i="4.98,1009,1392163200"; d="scan'208"; a="141619309" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 10 Jun 2014 14:21:33 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Tue, 10 Jun 2014 10:21:32 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WuMiB-0006am-0x; Tue, 10 Jun 2014 15:07:39 +0100 From: Stefano Stabellini To: Date: Tue, 10 Jun 2014 15:07:19 +0100 Message-ID: <1402409240-28114-11-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v9 11/12] xen/arm: introduce GIC_PRI_TO_GUEST macro X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: GICH_LR registers and GICH_VMCR only support 5 bits for guest irq priorities. Introduce a macro to reduce the 8-bit priority fields to 5 bits; use it in gic.c. Signed-off-by: Stefano Stabellini Acked-by: Ian Campbell --- Changes in v8: - fix typo and hard tabs. --- xen/arch/arm/gic.c | 2 +- xen/include/asm-arm/gic.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 29c0502..3728182 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -555,7 +555,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, BUG_ON(lr < 0); BUG_ON(state & ~(GICH_LR_STATE_MASK<priority >> 3) << GICH_LR_PRIORITY_SHIFT) | + lr_val = state | (GIC_PRI_TO_GUEST(p->priority) << GICH_LR_PRIORITY_SHIFT) | ((p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); if ( p->desc != NULL ) lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 0c4c583..aede45c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -149,6 +149,8 @@ #define GIC_PRI_IRQ 0xa0 #define GIC_PRI_IPI 0x90 /* IPIs must preempt normal interrupts */ #define GIC_PRI_HIGHEST 0x80 /* Higher priorities belong to Secure-World */ +#define GIC_PRI_TO_GUEST(pri) (pri >> 3) /* GICH_LR and GICH_VMCR only support + 5 bits for guest irq priority */ #ifndef __ASSEMBLY__