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[50.57.142.19]) by mx.google.com with ESMTPS id mv4si157640igb.15.2014.06.19.07.12.09 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 19 Jun 2014 07:12:10 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wxd2J-00088M-VN; Thu, 19 Jun 2014 14:09:55 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wxd2I-00088H-PR for xen-devel@lists.xenproject.org; Thu, 19 Jun 2014 14:09:54 +0000 Received: from [85.158.143.35:26081] by server-3.bemta-4.messagelabs.com id D4/4F-16194-23FE2A35; Thu, 19 Jun 2014 14:09:54 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-13.tower-21.messagelabs.com!1403186993!5201991!1 X-Originating-IP: [209.85.212.169] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11310 invoked from network); 19 Jun 2014 14:09:53 -0000 Received: from mail-wi0-f169.google.com (HELO mail-wi0-f169.google.com) (209.85.212.169) by server-13.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 19 Jun 2014 14:09:53 -0000 Received: by mail-wi0-f169.google.com with SMTP id hi2so10166984wib.4 for ; Thu, 19 Jun 2014 07:09:53 -0700 (PDT) X-Received: by 10.194.142.205 with SMTP id ry13mr5039149wjb.69.1403186992967; Thu, 19 Jun 2014 07:09:52 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id ho2sm11885129wib.15.2014.06.19.07.09.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jun 2014 07:09:52 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 19 Jun 2014 15:09:49 +0100 Message-Id: <1403186989-18871-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v2] xen/arm: Add some useful debug in coprocessor trapping X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: XSA-93 adds a couple of new functions to trap coprocessor registers. They unconditionally inject an undefined instruction to guest. When debugging an OS at early stage, it may be hard to know why the guest received an UNDEFINED. Add some debug message to help the developer when Xen is built in debug mode. Signed-off-by: Julien Grall --- Changes in v2: - Make the patch compile with debug=n - Fix typo in the commit message - Drop spurious change --- xen/arch/arm/traps.c | 20 ++++++++++++++++++++ xen/include/asm-arm/processor.h | 11 +++++++++++ 2 files changed, 31 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 7f77c56..069b9f3 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1546,23 +1546,43 @@ bad_cp: static void do_cp14_dbg(struct cpu_user_regs *regs, union hsr hsr) { +#ifndef NDEBUG + struct hsr_cp64 cp64 = hsr.cp64; +#endif + if ( !check_conditional_instr(regs, hsr) ) { advance_pc(regs, hsr); return; } +#ifndef NDEBUG + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); +#endif inject_undef32_exception(regs); } static void do_cp(struct cpu_user_regs *regs, union hsr hsr) { +#ifndef NDEBUG + struct hsr_cp cp = hsr.cp; +#endif + if ( !check_conditional_instr(regs, hsr) ) { advance_pc(regs, hsr); return; } +#ifndef NDEBUG + ASSERT(!cp.tas); /* We don't trap SIMD instruction */ + gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); +#endif inject_undef32_exception(regs); } diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index ebc683d..3be86f1 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -295,6 +295,17 @@ union hsr { unsigned long ec:6; /* Exception Class */ } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ + struct hsr_cp { + unsigned long coproc:4; /* Number of coproc accessed */ + unsigned long sbz0p:1; + unsigned long tas:1; /* Trapped Advanced SIMD */ + unsigned long res0:14; + unsigned long cc:4; /* Condition Code */ + unsigned long ccvalid:1;/* CC Valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } cp; /* HSR_EC_CP */ + #ifdef CONFIG_ARM_64 struct hsr_sysreg { unsigned long read:1; /* Direction */