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[50.57.142.19]) by mx.google.com with ESMTPS id k5si17566808wjf.30.2014.11.28.07.19.03 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 28 Nov 2014 07:19:04 -0800 (PST) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XuNIM-0003gf-Eb; Fri, 28 Nov 2014 15:17:18 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XuNIK-0003ga-Fa for xen-devel@lists.xenproject.org; Fri, 28 Nov 2014 15:17:16 +0000 Received: from [85.158.139.211] by server-1.bemta-5.messagelabs.com id 75/B4-24124-BF198745; Fri, 28 Nov 2014 15:17:15 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-10.tower-206.messagelabs.com!1417187833!8617071!1 X-Originating-IP: [209.85.212.174] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 6.12.4; banners=-,-,- X-VirusChecked: Checked Received: (qmail 28549 invoked from network); 28 Nov 2014 15:17:13 -0000 Received: from mail-wi0-f174.google.com (HELO mail-wi0-f174.google.com) (209.85.212.174) by server-10.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 28 Nov 2014 15:17:13 -0000 Received: by mail-wi0-f174.google.com with SMTP id h11so18905043wiw.1 for ; Fri, 28 Nov 2014 07:17:13 -0800 (PST) X-Received: by 10.180.80.133 with SMTP id r5mr60733815wix.20.1417187833102; Fri, 28 Nov 2014 07:17:13 -0800 (PST) Received: from chilopoda.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id d2sm15387726wjs.32.2014.11.28.07.17.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 28 Nov 2014 07:17:12 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Fri, 28 Nov 2014 15:17:06 +0000 Message-Id: <1417187826-5491-1-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.3 Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH] xen/arm: Handle platforms with edge-triggered virtual timer X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Some platforms (such as Xgene and ARMv8 models) use an edge-triggered interrupt for the virtual timer. Even if the timer output signal is masked in the context switch, the GIC will keep track that of any interrupts raised while IRQs are disabled. As soon as IRQs are re-enabled, the virtual interrupt timer will be injected to Xen. If an idle vVCPU was scheduled next then the interrupt handler doesn't expect to the receive the IRQ and will crash: (XEN) [<0000000000228388>] _spin_lock_irqsave+0x28/0x94 (PC) (XEN) [<0000000000228380>] _spin_lock_irqsave+0x20/0x94 (LR) (XEN) [<0000000000250510>] vgic_vcpu_inject_irq+0x40/0x1b0 (XEN) [<000000000024bcd0>] vtimer_interrupt+0x4c/0x54 (XEN) [<0000000000247010>] do_IRQ+0x1a4/0x220 (XEN) [<0000000000244864>] gic_interrupt+0x50/0xec (XEN) [<000000000024fbac>] do_trap_irq+0x20/0x2c (XEN) [<0000000000255240>] hyp_irq+0x5c/0x60 (XEN) [<0000000000241084>] context_switch+0xb8/0xc4 (XEN) [<000000000022482c>] schedule+0x684/0x6d0 (XEN) [<000000000022785c>] __do_softirq+0xcc/0xe8 (XEN) [<00000000002278d4>] do_softirq+0x14/0x1c (XEN) [<0000000000240fac>] idle_loop+0x134/0x154 (XEN) [<000000000024c160>] start_secondary+0x14c/0x15c (XEN) [<0000000000000001>] 0000000000000001 The proper solution is to context switch the virtual interrupt state at the GIC level. This would also avoid masking the output signal which requires specific handling in the guest OS and more complex code in Xen to deal with EOIs, and so is desirable for that reason too. Sadly, this solution requires some refactoring which would not be suitable for a freeze exception for the Xen 4.5 release. For now implement a temporary solution which ignores the virtual timer interrupt when the idle VCPU is running. Signed-off-by: Julien Grall --- Changes in v2: - Reword the commit message and comment in the code to explain the real bug. Based on Ian's reword. - Use unlikely This patch is a bug fix candidate for Xen 4.5 and backport for Xen 4.4. It affects at least Xgene platform and ARMv8 models where Xen may randomly crash. This patch don't inject the virtual timer interrupt if the current VCPU is the idle one. For now, I think this patch is the safest way to resolve the problem. I will work on a proper solution for Xen 4.6. --- xen/arch/arm/time.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index a6436f1..471d7a9 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -169,6 +169,19 @@ static void timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) { + /* + * Edge-triggered interrupt can be used for the virtual timer. Even + * if the timer output signal is masked in the context switch, the + * GIC will keep track that of any interrupts raised while IRQS as + * disabled. As soon as IRQs are re-enabled, the virtual interrupt + * will be injected to Xen. + * + * If an IDLE vCPU was scheduled next then we should ignore the + * interrupt. + */ + if ( unlikely(is_idle_vcpu(current)) ) + return; + current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL0); vgic_vcpu_inject_irq(current, current->arch.virt_timer.irq);