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([185.25.64.249]) by mx.google.com with ESMTPSA id dj5sm23172398wjb.28.2015.02.16.06.51.27 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 16 Feb 2015 06:51:28 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Mon, 16 Feb 2015 14:50:43 +0000 Message-Id: <1424098255-22490-4-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1424098255-22490-1-git-send-email-julien.grall@linaro.org> References: <1424098255-22490-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Vijaya.Kumar@caviumnetworks.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v3 03/15] xen/arm: vgic-v3: Correctly handle GICD_CTLR X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: As backward GICv2 compatibility is not supported in the vGICv3 driver, the bit ARE_NS is RAO/WI. Furthermore, when ARE_NS is set, the guest can only modify EnableGrp1A. At same time take the vgic_lock to write into domain.arch.vgic.ctrl. It was already taken during read. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v3: - Add Ian's ack Changes in v2: - Clearly explain that ARE_NS is RAO/WI rather than imply the guest should set it. - Typoes --- xen/arch/arm/vgic-v3.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e0a7d5b..9115199 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -45,6 +45,12 @@ #define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2 #define GICV3_GICR_PIDR4 GICV3_GICD_PIDR4 +/* + * GICD_CTLR default value: + * - No GICv2 compatibility => ARE = 1 + */ +#define VGICD_CTLR_DEFAULT (GICD_CTLR_ARE_NS) + static struct vcpu *vgic_v3_irouter_to_vcpu(struct vcpu *v, uint64_t irouter) { irouter &= ~(GICD_IROUTER_SPI_MODE_ANY); @@ -838,8 +844,15 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info) { case GICD_CTLR: if ( dabt.size != DABT_WORD ) goto bad_width; - /* Ignore all but the enable bit */ - v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE; + + vgic_lock(v); + /* Only EnableGrp1A can be changed */ + if ( *r & GICD_CTLR_ENABLE_G1A ) + v->domain->arch.vgic.ctlr |= GICD_CTLR_ENABLE_G1A; + else + v->domain->arch.vgic.ctlr &= ~GICD_CTLR_ENABLE_G1A; + vgic_unlock(v); + return 1; case GICD_TYPER: /* RO -- write ignored */ @@ -1100,6 +1113,8 @@ static int vgic_v3_domain_init(struct domain *d) register_mmio_handler(d, &vgic_rdistr_mmio_handler, d->arch.vgic.rbase[i], d->arch.vgic.rbase_size[i]); + d->arch.vgic.ctlr = VGICD_CTLR_DEFAULT; + return 0; }