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[192.237.175.120]) by mx.google.com with ESMTPS id v92si6461714iov.5.2017.10.09.06.26.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 06:26:07 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e1Y2T-00088m-18; Mon, 09 Oct 2017 13:24:09 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e1Y2R-000873-QU for xen-devel@lists.xen.org; Mon, 09 Oct 2017 13:24:07 +0000 Received: from [85.158.143.35] by server-5.bemta-6.messagelabs.com id 04/4F-03453-7787BD95; Mon, 09 Oct 2017 13:24:07 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRWlGSWpSXmKPExsVysyfVTbeg4na kwa8GeYslHxezODB6HN39mymAMYo1My8pvyKBNaP/2VuWgplSFd8nLmFvYDwr3MXIxSEksJlR 4s6fWWwQzmlGiYf7TjJ3MXJysAloStz5/IkJxBYRkJa49vkyI0gRs8B2Ronzc3+zgySEBdIkd mzaxQZiswioSsx7/hDM5hWwlPgwcwMjiC0hIC+xq+0iK4jNCRSftnk62AIhAQuJyx92sE5g5F 7AyLCKUaM4tagstUjX2FgvqSgzPaMkNzEzR9fQwEwvN7W4ODE9NScxqVgvOT93EyPQxwxAsIN x5/rAQ4ySHExKorxTCm5HCvEl5adUZiQWZ8QXleakFh9ilOHgUJLgrSwHygkWpaanVqRl5gCD DSYtwcGjJMLbD5LmLS5IzC3OTIdInWLU5ei4efcPkxBLXn5eqpQ473GQIgGQoozSPLgRsMC/x CgrJczLCHSUEE9BalFuZgmq/CtGcQ5GJWHeT2VAU3gy80rgNr0COoIJ6AjG4hsgR5QkIqSkGh iDTv77yWw/YSvXmkD5PqGZ+kvl1Q6V6RwxfFP2hrFI1SRRwKd28qY4jgLJ8gURB59PnKm40p+ xTbBn3zX5N97GLx885/sR6VLYxf3tecER7z09PldvfA6q2HrZuycjM+meHMethyJaz+f9NuIp XBo5dcfqxMB/aUHP16fpr3/YdNlqQW63VKQSS3FGoqEWc1FxIgD0SL5kdwIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-6.tower-21.messagelabs.com!1507555440!53249268!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 43220 invoked from network); 9 Oct 2017 13:24:00 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-6.tower-21.messagelabs.com with SMTP; 9 Oct 2017 13:24:00 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDA381529; Mon, 9 Oct 2017 06:23:59 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8AFED3F578; Mon, 9 Oct 2017 06:23:58 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 9 Oct 2017 14:23:41 +0100 Message-Id: <20171009132341.1678-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132341.1678-1-julien.grall@arm.com> References: <20171009132341.1678-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, Ross Lagerwall , Konrad Rzeszutek Wilk Subject: [Xen-devel] [PATCH v4 10/10] xen/arm: mm: Use memory flags for modify_xen_mappings rather than custom one X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" This will help to consolidate the page-table code and avoid different path depending on the action to perform. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara Reviewed-by: Stefano Stabellini Reviewed-by: Konrad Rzeszutek Wilk --- Cc: Konrad Rzeszutek Wilk Cc: Ross Lagerwall arch_livepatch_secure is now the same as on x86. It might be possible to combine both, but I left that alone for now. Changes in v4: - Add Konrad's reviewed-by Changes in v3: - Add Stefano's reviewed-by Changes in v2: - Add Andre's reviewed-by --- xen/arch/arm/livepatch.c | 6 +++--- xen/arch/arm/mm.c | 5 ++--- xen/include/asm-arm/page.h | 11 ----------- 3 files changed, 5 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/livepatch.c b/xen/arch/arm/livepatch.c index 3e53524365..279d52cc6c 100644 --- a/xen/arch/arm/livepatch.c +++ b/xen/arch/arm/livepatch.c @@ -146,15 +146,15 @@ int arch_livepatch_secure(const void *va, unsigned int pages, enum va_type type) switch ( type ) { case LIVEPATCH_VA_RX: - flags = PTE_RO; /* R set, NX clear */ + flags = PAGE_HYPERVISOR_RX; break; case LIVEPATCH_VA_RW: - flags = PTE_NX; /* R clear, NX set */ + flags = PAGE_HYPERVISOR_RW; break; case LIVEPATCH_VA_RO: - flags = PTE_NX | PTE_RO; /* R set, NX set */ + flags = PAGE_HYPERVISOR_RO; break; default: diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 2329ccee83..3c328e2df5 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -1041,8 +1041,8 @@ static int create_xen_entries(enum xenmap_operation op, else { pte = *entry; - pte.pt.ro = PTE_RO_MASK(flags); - pte.pt.xn = PTE_NX_MASK(flags); + pte.pt.ro = PAGE_RO_MASK(flags); + pte.pt.xn = PAGE_XN_MASK(flags); if ( !pte.pt.ro && !pte.pt.xn ) { printk("%s: Incorrect combination for addr=%lx\n", @@ -1085,7 +1085,6 @@ int destroy_xen_mappings(unsigned long v, unsigned long e) int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int flags) { - ASSERT((flags & (PTE_NX | PTE_RO)) == flags); return create_xen_entries(MODIFY, s, INVALID_MFN, (e - s) >> PAGE_SHIFT, flags); } diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index e2b3e402d0..e4be83a7bc 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -96,17 +96,6 @@ #define PAGE_HYPERVISOR_WC (_PAGE_DEVICE|MT_NORMAL_NC) /* - * Defines for changing the hypervisor PTE .ro and .nx bits. This is only to be - * used with modify_xen_mappings. - */ -#define _PTE_NX_BIT 0U -#define _PTE_RO_BIT 1U -#define PTE_NX (1U << _PTE_NX_BIT) -#define PTE_RO (1U << _PTE_RO_BIT) -#define PTE_NX_MASK(x) (((x) >> _PTE_NX_BIT) & 0x1U) -#define PTE_RO_MASK(x) (((x) >> _PTE_RO_BIT) & 0x1U) - -/* * Stage 2 Memory Type. * * These are valid in the MemAttr[3:0] field of an LPAE stage 2 page