From patchwork Fri Jan 19 13:41:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125371 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1055753ljf; Mon, 22 Jan 2018 01:31:09 -0800 (PST) X-Google-Smtp-Source: AH8x2251fG/4NMicbe+AlW2f7FFT+85oxza97ep5RPHKVznV8SzvhPVQBvdyP6BLvpNICklmcOTy X-Received: by 10.107.59.87 with SMTP id i84mr6632005ioa.99.1516613469802; Mon, 22 Jan 2018 01:31:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516613469; cv=none; d=google.com; s=arc-20160816; b=KcPJ2xUmrMFBKlIqPeG0wD2vYOko+KvGCF0TlszdjK5KVC0ObvUG54FHgQg+vSZsat JCdH+dOYlD+BtEAtiofm5wdXwUM2/aR5eIjy9EMaTPKCHtU+YU2OoDuqvKv8KIsmi2BW lmnH61BlPIXL7HoMLC48ZG9j2pXWLOhhbI6ttbeWPZYw975wkSPuIFrxrFTrpV0NYfMI bmbMYY+eSgZr0ZhdMjtXLBAtCSQZp1QLid/seEDmHahtcWoEWZK6VIv/2nrZvO0wLTWy wIbD0GG6rU5aGaJXdoqRVoTogpF+s/0alJAl9yc4XS12P74ue7IV0aQniPFSKEn0l/Bc bEqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=pUoQhZhyEa9ejzZ45eHS6/MTQPMJZC/o5MyoqhYS5Pg=; b=DEJTiS3YbJMdC8K0lpOEa1luhbGrLlEvW+ecJYDyT9VPUAteXmY3t/IO370A9qWZqL SPYjsNFs2Xooum+bkqe4jskB1cGhskZnQyjJTep5v/3OMtlaVU/eGwkO6iHCFwIZcPmi egOAAvdSvN9OfCHY3XLWsqjs2VEG8+jr/o2BHLfViwvbIXtXG54w09iL3KNLSGbHTnHR ohTdlZuXUwcSWWzOvSHQuq23/VnMe7iRDsPXIDCWWZ0gGPkmMnvuFLUqih6OmOxmnTeD VRy5gBtLubgMC7ZuR/MdmUTHqh3oqEZXzCu1LkM7STXSdGjnGWj/j/qg25/0W5iafxhk QYOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IuqWHEED; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r62si5651857itg.35.2018.01.22.01.31.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jan 2018 01:31:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IuqWHEED; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1edYOg-0001sn-Ss; Mon, 22 Jan 2018 09:28:10 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1edYOg-0001sh-0d for xen-devel@lists.xen.org; Mon, 22 Jan 2018 09:28:10 +0000 X-Inumbo-ID: 8cd2bcc0-ff56-11e7-ba59-bc764e045a96 Received: from mail-wr0-x242.google.com (unknown [2a00:1450:400c:c0c::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 8cd2bcc0-ff56-11e7-ba59-bc764e045a96; Mon, 22 Jan 2018 10:28:06 +0100 (CET) Received: by mail-wr0-x242.google.com with SMTP id g21so7807856wrb.13 for ; Mon, 22 Jan 2018 01:28:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gOdEzGyfOsrSClsrr0dvYywk8hzJrtFR4HQpiieVJSE=; b=IuqWHEED1bS8jwPfCRkNB/PQV9AccrvuQa90z5Se6wyO+G6m/DKMQWFb82L1WLV/Wn kOyuZnDf/iqEk4ABf4CCbXL7IDcvx7/0Y7E7u92P9UGrMRKmHxC4nUO92PtdsPmCXphM HJ6RQ3wxxH9Gj9ceKfGtveivb1psBH1ON8BvA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gOdEzGyfOsrSClsrr0dvYywk8hzJrtFR4HQpiieVJSE=; b=ir+rPn9W32ViwmeS/t3fIihrqJaZDnaOKWE+ExZSIzcBuSjffsnM0To02L7moobW5E S5gTZT5yo+qF4MfRibmT8ralTohE5it+TMl2L0YsQl+LZDgVN35ObS2/HYV+4zwrVdoA foWzxG/9XLXYgdxoxcKdxIrzP+lgoVbohP6Z8Awn+7qOdAtaBiVtUzXnGONV33vrF/u7 RfZBaINH72ClARF1RD8AAyXLexqjvevZZGHS1YEFpdPLydOKJHUw4P7PugVavnrUSk/m TVTIzJhzrBRo+Qf+VOvpmh1Qfcfmvn/avpqWTSuFiFJHP1C1HfOjV9l3XIfBNup+ZqN0 fMsg== X-Gm-Message-State: AKwxytefBdd9JeacqunBymFjVSRaooNpqKubS5tSfottRRLH8MaxeLHW BWZfMW0BjL6Z0KNXpPQp9H98vgtRgb4= X-Received: by 10.223.152.109 with SMTP id v100mr9026536wrb.222.1516369268740; Fri, 19 Jan 2018 05:41:08 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:08 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:41:00 +0000 Message-Id: <20180119134103.3390-5-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 4/7] xen/arm32: Add skeleton to harden branch predictor aliasing attacks X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Aliasing attacked against CPU branch predictors can allow an attacker to redirect speculative control flow on some CPUs and potentially divulge information from one context to another. This patch adds initiatial skeleton code behind a new Kconfig option to enable implementation-specific mitigations against these attacks for CPUs that are affected. Most of mitigations will have to be applied when entering to the hypervisor from the guest context. Because the attack is against branch predictor, it is not possible to safely use branch instruction before the mitigation is applied. Therefore this has to be done in the vector entry before jump to the helper handling a given exception. However, on arm32, each vector contain a single instruction. This means that the hardened vector tables may rely on the state of registers that does not hold when in the hypervisor (e.g SP is 8 bytes aligned). Therefore hypervisor code running with guest vectors table should be minimized and always have interrupts masked to reduce the risk to use them. This patch provides an infrastructure to switch vector tables before entering to the guest and when leaving it. Note that alternative could have been used, but older Xen (4.8 or earlier) doesn't have support. So avoid using alternative to ease backporting. This is part of XSA-254. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/Kconfig | 3 +++ xen/arch/arm/arm32/entry.S | 41 ++++++++++++++++++++++++++++++++++++++++- xen/arch/arm/cpuerrata.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 06fd85cc77..2782ee6589 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -191,6 +191,9 @@ config HARDEN_BRANCH_PREDICTOR config ARM64_HARDEN_BRANCH_PREDICTOR def_bool y if ARM_64 && HARDEN_BRANCH_PREDICTOR +config ARM32_HARDEN_BRANCH_PREDICTOR + def_bool y if ARM_32 && HARDEN_BRANCH_PREDICTOR + source "common/Kconfig" source "drivers/Kconfig" diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index c2fad5fe9b..54a1733f87 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -34,6 +34,20 @@ blne save_guest_regs save_guest_regs: +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + /* + * Restore vectors table to the default as it may have been + * changed when returning to the guest (see + * return_to_hypervisor). We need to do that early (e.g before + * any interrupts are unmasked) because hardened vectors requires + * SP to be 8 bytes aligned. This does not hold when running in + * the hypervisor. + */ + ldr r1, =hyp_traps_vector + mcr p15, 4, r1, c12, c0, 0 + isb +#endif + ldr r11, =0xffffffff /* Clobber SP which is only valid for hypervisor frames. */ str r11, [sp, #UREGS_sp] SAVE_ONE_BANKED(SP_usr) @@ -179,12 +193,37 @@ return_to_guest: RESTORE_ONE_BANKED(R11_fiq); RESTORE_ONE_BANKED(R12_fiq); /* Fall thru */ return_to_hypervisor: - cpsid i + cpsid ai ldr lr, [sp, #UREGS_lr] ldr r11, [sp, #UREGS_pc] msr ELR_hyp, r11 ldr r11, [sp, #UREGS_cpsr] msr SPSR_hyp, r11 +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + /* + * Hardening branch predictor may require to setup a different + * vector tables before returning to the guests. Those vectors + * may rely on the state of registers that does not hold when + * running in the hypervisor (e.g SP is 8 bytes aligned). So setup + * HVBAR very late. + * + * Default vectors table will be restored on exit (see + * save_guest_regs). + */ + mov r9, #0 /* vector tables = NULL */ + /* + * Load vector tables pointer from the per-cpu bp_harden_vecs + * when returning to the guest only. + */ + and r11, #PSR_MODE_MASK + cmp r11, #PSR_MODE_HYP + ldrne r11, =per_cpu__bp_harden_vecs + mrcne p15, 4, r10, c13, c0, 2 /* r10 = per-cpu offset (HTPIDR) */ + addne r11, r11, r10 /* r11 = offset of the vector tables */ + ldrne r9, [r11] /* r9 = vector tables */ + cmp r9, #0 /* Only update HVBAR when the vector */ + mcrne p15, 4, r9, c12, c0, 0 /* tables is not NULL. */ +#endif pop {r0-r12} add sp, #(UREGS_SP_usr - UREGS_sp); /* SP, LR, SPSR, PC */ clrex diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index f1ea7f3c5b..0a138fa735 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -170,6 +170,36 @@ static int enable_psci_bp_hardening(void *data) #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ +/* Hardening Branch predictor code for Arm32 */ +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + +/* + * Per-CPU vector tables to use when returning to the guests. They will + * only be used on platform requiring to harden the branch predictor. + */ +DEFINE_PER_CPU_READ_MOSTLY(const char *, bp_harden_vecs); + +extern char hyp_traps_vector_bp_inv[]; + +static void __maybe_unused +install_bp_hardening_vecs(const struct arm_cpu_capabilities *entry, + const char *hyp_vecs, const char *desc) +{ + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return; + + printk(XENLOG_INFO "CPU%u will %s on guest exit\n", + smp_processor_id(), desc); + this_cpu(bp_harden_vecs) = hyp_vecs; +} + +#endif + #define MIDR_RANGE(model, min, max) \ .matches = is_affected_midr_range, \ .midr_model = model, \