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a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1579530220; bh=QLJog4DfYyxTa/pGhw8zE2jdA/xz/qI7iFpPR8p4Zno=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=OK/DzpV4HbhmKsexkuMvmA+q3VySwGYKQRrylVrBUtDATeRaxSP5ESUf9CLgPpKfN 9G/FyJkD+6uAxeRL3vBBRW5hMmIuoggLp6wT/tAdXfrtry2Xm0MOj6jA0Q8q1Wwxmp 92GGVO6XLpzTmT6S2/UIU4Vnzlypu+AjhMT7fb85Nlu3rgZvtaC1uRrdMGWNjIadMP KAA8cINzkNN5xI/RY7pqDCim7t3pKJBYER+EEhPAgl4jM8Zkv5RUxRKSK7STW9dyh9 X7MPNRU+tq7o/Hx4H774UPIVXKmclkoZJI4o/P+l4ng1ZV8/GzP5r+tj25mWQtbKDT YwZn5Mfuir6Ig== Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, atalambedu@nvidia.com, linux-kernel@vger.kernel.org, Sameer Pujar , lgirdwood@gmail.com, jonathanh@nvidia.com, viswanathl@nvidia.com, sharadg@nvidia.com, broonie@kernel.org, thierry.reding@gmail.com, linux-tegra@vger.kernel.org, rlokhande@nvidia.com, mkumard@nvidia.com, dramesh@nvidia.com Subject: [alsa-devel] [PATCH 9/9] arm64: tegra: enable AHUB modules for few Tegra chips X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" This patch enables AHUB, ADMAIF modules for following Tegra platforms. Along with this specific instances of I/O modules are enabled as per the board design. * Jetson TX1 - I2S1, I2S2, I2S3, I2S4 and I2S5 - DMIC1, DMIC2 and DMIC3 * Jetson TX2 - I2S1, I2S2, I2S3, I2S4, I2S5 and I2S6 - DMIC1, DMIC2 and DMIC3 - DSPK2 * Jetson AGX Xavier - I2S1, I2S2, I2S4 and I2S6 - DMIC2 and DMIC3 - DSPK1 Signed-off-by: Sameer Pujar --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 48 ++++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 36 ++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 40 ++++++++++++++++++ 3 files changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index f1de4ff..717993c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -20,6 +20,54 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + admaif@290f000 { + status = "okay"; + }; + + i2s@2901000 { + status = "okay"; + }; + + i2s@2901100 { + status = "okay"; + }; + + i2s@2901200 { + status = "okay"; + }; + + i2s@2901300 { + status = "okay"; + }; + + i2s@2901400 { + status = "okay"; + }; + + i2s@2901500 { + status = "okay"; + }; + + dmic@2904000 { + status = "okay"; + }; + + dmic@2904100 { + status = "okay"; + }; + + dmic@2904200 { + status = "okay"; + }; + + dspk@2905100 { + status = "okay"; + }; + }; }; i2c@3160000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 985e7d8..f5d5832 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -21,6 +21,42 @@ interrupt-controller@2a40000 { status = "okay"; }; + + ahub@2900800 { + status = "okay"; + + admaif@290f000 { + status = "okay"; + }; + + i2s@2901000 { + status = "okay"; + }; + + i2s@2901100 { + status = "okay"; + }; + + i2s@2901300 { + status = "okay"; + }; + + i2s@2901500 { + status = "okay"; + }; + + dmic@2904100 { + status = "okay"; + }; + + dmic@2904200 { + status = "okay"; + }; + + dspk@2905000 { + status = "okay"; + }; + }; }; ddc: i2c@31c0000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index a3cafe3..c8d2c21 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -123,5 +123,45 @@ agic@702f9000 { status = "okay"; }; + + ahub@702d0800 { + status = "okay"; + + admaif@702d0000 { + status = "okay"; + }; + + i2s@702d1000 { + status = "okay"; + }; + + i2s@702d1100 { + status = "okay"; + }; + + i2s@702d1200 { + status = "okay"; + }; + + i2s@702d1300 { + status = "okay"; + }; + + i2s@702d1400 { + status = "okay"; + }; + + dmic@702d4000 { + status = "okay"; + }; + + dmic@702d4100 { + status = "okay"; + }; + + dmic@702d4200 { + status = "okay"; + }; + }; }; };