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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(40470700004)(110136005)(40460700003)(8676002)(316002)(7416002)(107886003)(36860700001)(6666004)(82310400004)(8936002)(5660300002)(4326008)(47076005)(54906003)(36756003)(81166007)(70206006)(86362001)(356005)(70586007)(336012)(508600001)(2616005)(426003)(2906002)(186003)(26005)(7696005)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2022 08:48:51.6974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83a97894-af8e-46b7-7ded-08d9dfdf8303 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5284 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Sameer Pujar , linux-kernel@vger.kernel.org, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, mkumard@nvidia.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Mohan Kumar The register offsets of switches connecting various AHUB internal modules have changed from previous chip. Address this variation by making use of Tegra234 based compatible. Signed-off-by: Mohan Kumar Signed-off-by: Sameer Pujar --- sound/soc/tegra/tegra210_ahub.c | 147 +++++++++++++++++++++++++++++++++++++++- sound/soc/tegra/tegra210_ahub.h | 4 +- 2 files changed, 149 insertions(+), 2 deletions(-) diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahub.c index 63676fb..523f983 100644 --- a/sound/soc/tegra/tegra210_ahub.c +++ b/sound/soc/tegra/tegra210_ahub.c @@ -2,7 +2,7 @@ // // tegra210_ahub.c - Tegra210 AHUB driver // -// Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. +// Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. #include #include @@ -624,6 +624,35 @@ MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); +/* Controls for t234 */ +MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44); +MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45); +MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48); +MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49); +MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a); +MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b); +MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c); +MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d); +MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e); +MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f); +MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50); +MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51); +MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52); +MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53); +MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58); +MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59); +MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a); +MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b); +MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c); +MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d); +MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e); +MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f); +MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60); +MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61); +MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62); +MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63); + + static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { WIDGETS("ADMAIF1", t210_admaif1_tx), WIDGETS("ADMAIF2", t210_admaif2_tx), @@ -782,6 +811,102 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { TX_WIDGETS("MIXER1 TX5"), }; +static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = { + WIDGETS("ADMAIF1", t186_admaif1_tx), + WIDGETS("ADMAIF2", t186_admaif2_tx), + WIDGETS("ADMAIF3", t186_admaif3_tx), + WIDGETS("ADMAIF4", t186_admaif4_tx), + WIDGETS("ADMAIF5", t186_admaif5_tx), + WIDGETS("ADMAIF6", t186_admaif6_tx), + WIDGETS("ADMAIF7", t186_admaif7_tx), + WIDGETS("ADMAIF8", t186_admaif8_tx), + WIDGETS("ADMAIF9", t186_admaif9_tx), + WIDGETS("ADMAIF10", t186_admaif10_tx), + WIDGETS("ADMAIF11", t186_admaif11_tx), + WIDGETS("ADMAIF12", t186_admaif12_tx), + WIDGETS("ADMAIF13", t186_admaif13_tx), + WIDGETS("ADMAIF14", t186_admaif14_tx), + WIDGETS("ADMAIF15", t186_admaif15_tx), + WIDGETS("ADMAIF16", t186_admaif16_tx), + WIDGETS("ADMAIF17", t234_admaif17_tx), + WIDGETS("ADMAIF18", t234_admaif18_tx), + WIDGETS("ADMAIF19", t234_admaif19_tx), + WIDGETS("ADMAIF20", t234_admaif20_tx), + WIDGETS("I2S1", t186_i2s1_tx), + WIDGETS("I2S2", t186_i2s2_tx), + WIDGETS("I2S3", t186_i2s3_tx), + WIDGETS("I2S4", t186_i2s4_tx), + WIDGETS("I2S5", t186_i2s5_tx), + WIDGETS("I2S6", t186_i2s6_tx), + TX_WIDGETS("DMIC1"), + TX_WIDGETS("DMIC2"), + TX_WIDGETS("DMIC3"), + TX_WIDGETS("DMIC4"), + WIDGETS("DSPK1", t186_dspk1_tx), + WIDGETS("DSPK2", t186_dspk2_tx), + WIDGETS("SFC1", t186_sfc1_tx), + WIDGETS("SFC2", t186_sfc2_tx), + WIDGETS("SFC3", t186_sfc3_tx), + WIDGETS("SFC4", t186_sfc4_tx), + WIDGETS("MVC1", t234_mvc1_tx), + WIDGETS("MVC2", t234_mvc2_tx), + WIDGETS("AMX1 RX1", t234_amx11_tx), + WIDGETS("AMX1 RX2", t234_amx12_tx), + WIDGETS("AMX1 RX3", t234_amx13_tx), + WIDGETS("AMX1 RX4", t234_amx14_tx), + WIDGETS("AMX2 RX1", t234_amx21_tx), + WIDGETS("AMX2 RX2", t234_amx22_tx), + WIDGETS("AMX2 RX3", t234_amx23_tx), + WIDGETS("AMX2 RX4", t234_amx24_tx), + WIDGETS("AMX3 RX1", t234_amx31_tx), + WIDGETS("AMX3 RX2", t234_amx32_tx), + WIDGETS("AMX3 RX3", t234_amx33_tx), + WIDGETS("AMX3 RX4", t234_amx34_tx), + WIDGETS("AMX4 RX1", t234_amx41_tx), + WIDGETS("AMX4 RX2", t234_amx42_tx), + WIDGETS("AMX4 RX3", t234_amx43_tx), + WIDGETS("AMX4 RX4", t234_amx44_tx), + TX_WIDGETS("AMX1"), + TX_WIDGETS("AMX2"), + TX_WIDGETS("AMX3"), + TX_WIDGETS("AMX4"), + WIDGETS("ADX1", t234_adx1_tx), + WIDGETS("ADX2", t234_adx2_tx), + WIDGETS("ADX3", t234_adx3_tx), + WIDGETS("ADX4", t234_adx4_tx), + TX_WIDGETS("ADX1 TX1"), + TX_WIDGETS("ADX1 TX2"), + TX_WIDGETS("ADX1 TX3"), + TX_WIDGETS("ADX1 TX4"), + TX_WIDGETS("ADX2 TX1"), + TX_WIDGETS("ADX2 TX2"), + TX_WIDGETS("ADX2 TX3"), + TX_WIDGETS("ADX2 TX4"), + TX_WIDGETS("ADX3 TX1"), + TX_WIDGETS("ADX3 TX2"), + TX_WIDGETS("ADX3 TX3"), + TX_WIDGETS("ADX3 TX4"), + TX_WIDGETS("ADX4 TX1"), + TX_WIDGETS("ADX4 TX2"), + TX_WIDGETS("ADX4 TX3"), + TX_WIDGETS("ADX4 TX4"), + WIDGETS("MIXER1 RX1", t186_mixer11_tx), + WIDGETS("MIXER1 RX2", t186_mixer12_tx), + WIDGETS("MIXER1 RX3", t186_mixer13_tx), + WIDGETS("MIXER1 RX4", t186_mixer14_tx), + WIDGETS("MIXER1 RX5", t186_mixer15_tx), + WIDGETS("MIXER1 RX6", t186_mixer16_tx), + WIDGETS("MIXER1 RX7", t186_mixer17_tx), + WIDGETS("MIXER1 RX8", t186_mixer18_tx), + WIDGETS("MIXER1 RX9", t186_mixer19_tx), + WIDGETS("MIXER1 RX10", t186_mixer110_tx), + TX_WIDGETS("MIXER1 TX1"), + TX_WIDGETS("MIXER1 TX2"), + TX_WIDGETS("MIXER1 TX3"), + TX_WIDGETS("MIXER1 TX4"), + TX_WIDGETS("MIXER1 TX5"), +}; + #define TEGRA_COMMON_MUX_ROUTES(name) \ { name " XBAR-TX", NULL, name " Mux" }, \ { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \ @@ -1017,6 +1142,13 @@ static const struct snd_soc_component_driver tegra186_ahub_component = { .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), }; +static const struct snd_soc_component_driver tegra234_ahub_component = { + .dapm_widgets = tegra234_ahub_widgets, + .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets), + .dapm_routes = tegra186_ahub_routes, + .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), +}; + static const struct regmap_config tegra210_ahub_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -1057,9 +1189,22 @@ static const struct tegra_ahub_soc_data soc_data_tegra186 = { .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, }; +static const struct tegra_ahub_soc_data soc_data_tegra234 = { + .cmpnt_drv = &tegra234_ahub_component, + .dai_drv = tegra186_ahub_dais, + .num_dais = ARRAY_SIZE(tegra186_ahub_dais), + .regmap_config = &tegra186_ahub_regmap_config, + .mask[0] = TEGRA186_XBAR_REG_MASK_0, + .mask[1] = TEGRA186_XBAR_REG_MASK_1, + .mask[2] = TEGRA186_XBAR_REG_MASK_2, + .mask[3] = TEGRA186_XBAR_REG_MASK_3, + .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, +}; + static const struct of_device_id tegra_ahub_of_match[] = { { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 }, { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 }, + { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 }, {}, }; MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); diff --git a/sound/soc/tegra/tegra210_ahub.h b/sound/soc/tegra/tegra210_ahub.h index 47802bbe..2728db4 100644 --- a/sound/soc/tegra/tegra210_ahub.h +++ b/sound/soc/tegra/tegra210_ahub.h @@ -2,7 +2,7 @@ /* * tegra210_ahub.h - TEGRA210 AHUB * - * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * */ @@ -74,6 +74,8 @@ tegra_ahub_get_value_enum, \ tegra_ahub_put_value_enum) +#define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id) + #define WIDGETS(sname, ename) \ SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \