From patchwork Wed Nov 30 11:15:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiong Wang X-Patchwork-Id: 85000 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp180416qgi; Wed, 30 Nov 2016 03:16:28 -0800 (PST) X-Received: by 10.84.214.1 with SMTP id h1mr72908904pli.47.1480504588849; Wed, 30 Nov 2016 03:16:28 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id w17si49757893pgh.156.2016.11.30.03.16.28 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Nov 2016 03:16:28 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-return-94656-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of binutils-return-94656-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=binutils-return-94656-patch=linaro.org@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:to:references:cc:from:message-id:date :mime-version:in-reply-to:content-type; q=dns; s=default; b=viCk uwKkKwfY9pMgLr1Kkv/hvLrsBuuyi8J99+jgZFwbhHkMqOKLvJ+yrJot8DcnZn40 B9aYMIcTEg1ZvlHENV+SkcqdbAL/MbtnNP1KyKemSxSJfwpyB7PAh/Qo0YmGCAyU 0Xt6zPZ/+1LxveSqgbgfWgZWZZo9ShW3iOQtPvk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:to:references:cc:from:message-id:date :mime-version:in-reply-to:content-type; s=default; bh=BMQQQrSPkN fCSLeh4NFZJcM4Msg=; b=okZRPSaasiVA3aUsey8SLaX1xqMH4zaZ4TbvmwLp3O nlPFyzb31HCGg5tdRKG4EsC2JU1mXrs/nxqaATIbpOrRiEP0A6REyc7Br4UT7acA dpvBw9H0OKaihO3wEwolP+vfS9Z9pYmK3/mt3cRPmDnmDZe/re8asj89MSbir6pO U= Received: (qmail 84121 invoked by alias); 30 Nov 2016 11:15:43 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 84031 invoked by uid 89); 30 Nov 2016 11:15:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Binutils, signing, dwarf2.def, UD:dwarf2.def X-Spam-User: qpsmtpd, 2 recipients X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 30 Nov 2016 11:15:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7263A16; Wed, 30 Nov 2016 03:15:25 -0800 (PST) Received: from [10.2.206.198] (e104437-lin.cambridge.arm.com [10.2.206.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6D0BA3F445; Wed, 30 Nov 2016 03:15:24 -0800 (PST) Subject: Re: [1/9][RFC][DWARF] Reserve three DW_OP numbers in vendor extension space To: Jakub Jelinek , Mark Wielaard References: <72418e98-a400-c503-e8ce-c3fbe1ecc4a7@foss.arm.com> <20161111193859.GJ3541@tucnak.redhat.com> <20161115161817.GL3541@tucnak.redhat.com> <5896be40-51de-55f7-f4a1-4c5af7ff9aec@foss.arm.com> <1479304496.14569.256.camel@redhat.com> <20161116140218.GU3541@tucnak.redhat.com> Cc: "Richard Earnshaw (lists)" , gcc-patches , gdb-patches@sourceware.org, Binutils From: Jiong Wang Message-ID: <07b84003-4e73-8a7f-f949-4c3500e4ffc4@foss.arm.com> Date: Wed, 30 Nov 2016 11:15:22 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.0 MIME-Version: 1.0 In-Reply-To: <20161116140218.GU3541@tucnak.redhat.com> X-IsSubscribed: yes On 16/11/16 14:02, Jakub Jelinek wrote: > On Wed, Nov 16, 2016 at 02:54:56PM +0100, Mark Wielaard wrote: >> On Wed, 2016-11-16 at 10:00 +0000, Jiong Wang wrote: >>> The two operations DW_OP_AARCH64_paciasp and DW_OP_AARCH64_paciasp_deref were >>> designed as shortcut operations when LR is signed with A key and using >>> function's CFA as salt. This is the default behaviour of return address >>> signing so is expected to be used for most of the time. DW_OP_AARCH64_pauth >>> is designed as a generic operation that allow describing pointer signing on >>> any value using any salt and key in case we can't use the shortcut operations >>> we can use this. >> >> I admit to not fully understand the salting/keying involved. But given >> that the DW_OP space is really tiny, so we would like to not eat up too >> many of them for new opcodes. And given that introducing any new DW_OPs >> using for CFI unwinding will break any unwinder anyway causing us to >> update them all for this new feature. Have you thought about using a new >> CIE augmentation string character for describing that the return >> address/link register used by a function/frame is salted/keyed? >> >> This seems a good description of CIE records and augmentation >> characters:http://www.airs.com/blog/archives/460 >> >> It obviously also involves updating all unwinders to understand the new >> augmentation character (and possible arguments). But it might be more >> generic and saves us from using up too many DW_OPs. > > From what I understood, the return address is not always scrambled, so > it doesn't apply to the whole function, just to most of it (except for > an insn in the prologue and some in the epilogue). So I think one op is > needed. But can't it be just a toggable flag whether the return address > is scrambled + some arguments to it? > Thus DW_OP_AARCH64_scramble .uleb128 0 would mean that the default > way of scrambling starts here (if not already active) or any kind of > scrambling ends here (if already active), and > DW_OP_AARCH64_scramble .uleb128 non-zero would be whatever encoding you need > to represent details of the less common variants with details what to do. > Then you'd just hook through some MD_* macro in the unwinder the > descrambling operation if the scrambling is active at the insns you unwind > on. > > Jakub Hi Mark, Jakub: Thanks very much for the suggestions. I have done some experiments on your ideas and am thinking it's good to combine them together. The use of DW_CFA instead of DW_OP can avoid building all information from scratch at each unwind location, while we can indicate the signing key index through new AArch64 CIE augmentation 'B'. This new approach reduce the unwind table size overhead from ~25% to ~5% when return address signing enabled, it also largely simplified dwarf generation code for return address signing. As one new DWARF call frame instruction is needed for AArch64, I want to reuse DW_CFA_GNU_window_save to save the space. It is in vendor extension space and used for Sparc only, I think it make sense to reuse it for AArch64. On AArch64, DW_CFA_GNU_window_save toggle return address sign status which kept in a new boolean type column in DWARF table, so DW_CFA_GNU_window_save takes no argument on AArch64, the same as on Sparc, this makes no difference to those existed encoding, length calculation code. Meanwhile one new DWARF expression operation number is still needed for AArch64, it's useful for describing those complex pointer signing scenarios and it will be used to multiplex some further extensions on AArch64. OK on this proposal and to install this patch to gcc trunk? Hi GDB, Binutils maintainer: OK on this proposal and install this patch to binutils-gdb master? include/ 2016-11-29 Richard Earnshaw Jiong Wang * dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea. diff --git a/include/dwarf2.def b/include/dwarf2.def index bb916ca238221151cf49359c25fd92643c7e60af..f3892a20da1fe13ddb419e5d7eda07f2c8d8b0c6 100644 --- a/include/dwarf2.def +++ b/include/dwarf2.def @@ -684,6 +684,12 @@ DW_OP (DW_OP_HP_unmod_range, 0xe5) DW_OP (DW_OP_HP_tls, 0xe6) /* PGI (STMicroelectronics) extensions. */ DW_OP (DW_OP_PGI_omp_thread_num, 0xf8) +/* AARCH64 extensions. + DW_OP_AARCH64_operation takes one mandatory unsigned LEB128 operand. + Bits[6:0] of this operand is the action code, all others bits are initialized + to 0 except explicitly documented for one action. Please refer AArch64 DWARF + ABI documentation for details. */ +DW_OP (DW_OP_AARCH64_operation, 0xea) DW_END_OP DW_FIRST_ATE (DW_ATE_void, 0x0) @@ -765,7 +771,8 @@ DW_CFA (DW_CFA_hi_user, 0x3f) /* SGI/MIPS specific. */ DW_CFA (DW_CFA_MIPS_advance_loc8, 0x1d) -/* GNU extensions. */ +/* GNU extensions. + NOTE: DW_CFA_GNU_window_save is multiplexed on Sparc and AArch64. */ DW_CFA (DW_CFA_GNU_window_save, 0x2d) DW_CFA (DW_CFA_GNU_args_size, 0x2e) DW_CFA (DW_CFA_GNU_negative_offset_extended, 0x2f)